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Class Information
Number: 438/645
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Diverse conductors > Having planarization step
Description: Processes wherein a material layer is leveled into a single plane at any stage in the process.










Sub-classes under this class:

Class Number Class Name Patents
438/646 Utilizing reflow 101


Patents under this class:
1 2 3 4 5 6 7

Patent Number Title Of Patent Date Issued
8703612 Process for forming contact plugs Apr. 22, 2014
8685853 Dual damascene copper process using a selected mask Apr. 1, 2014
8673772 Biosensor chip and a method of manufacturing the same Mar. 18, 2014
8664766 Interconnect structure containing non-damaged dielectric and a via gouging feature Mar. 4, 2014
8580687 Semiconductor structure and method for making same Nov. 12, 2013
8541300 Method of manufacturing semiconductor device, semiconductor device thus manufactured, and semiconductor manufacturing apparatus Sep. 24, 2013
8491807 Abrasive liquid for metal and method for polishing Jul. 23, 2013
8461040 Method of forming shielded gate power transistor utilizing chemical mechanical planarization Jun. 11, 2013
8455350 Integrated circuit system employing gate shield and/or ground shield Jun. 4, 2013
8450197 Contact elements of a semiconductor device formed by electroless plating and excess material removal with reduced sheer forces May. 28, 2013
8435885 Method and system for extracting samples after patterning of microstructure devices May. 7, 2013
8373070 Metal structure of flexible multi-layer substrate and manufacturing method thereof Feb. 12, 2013
8361832 Contact for memory cell Jan. 29, 2013
8349729 Hybrid bonding interface for 3-dimensional chip integration Jan. 8, 2013
8349731 Methods for forming copper diffusion barriers for semiconductor interconnect structures Jan. 8, 2013
8212359 Semiconductor integrated circuit device, mounting structure of semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device Jul. 3, 2012
8188380 Printed wiring board and method for manufacturing printed wiring board May. 29, 2012
8129278 Chemical mechanical polishing process Mar. 6, 2012
8105942 CMP-first damascene process scheme Jan. 31, 2012
8097526 Accessing or interconnecting integrated circuits Jan. 17, 2012
8053357 Prevention of post CMP defects in CU/FSG process Nov. 8, 2011
8043963 Semiconductor device manufacturing method and semiconductor device manufacturing apparatus Oct. 25, 2011
8038898 Abrasive liquid for metal and method for polishing Oct. 18, 2011
8030209 Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer Oct. 4, 2011
7989341 Dual damascence copper process using a selected mask Aug. 2, 2011
7972956 Method for manufacturing a wire structure of a semiconductor device Jul. 5, 2011
7968456 Method of forming an embedded barrier layer for protection from chemical mechanical polishing process Jun. 28, 2011
7960277 Electronic device and method of manufacturing the same Jun. 14, 2011
7935625 Method of forming a metal line of a semiconductor memory device May. 3, 2011
7928007 Method for reducing dielectric overetch when making contact to conductive features Apr. 19, 2011
7915161 Post passivation interconnection schemes on top of IC chip Mar. 29, 2011
7910477 Etch residue reduction by ash methodology Mar. 22, 2011
7902068 Manufacturing method of semiconductor device Mar. 8, 2011
7897509 Semiconductor wafer and method of manufacturing the same and method of manufacturing semiconductor device Mar. 1, 2011
7867870 Semiconductor device and method for forming device isolation film of semiconductor device Jan. 11, 2011
7846834 Interconnect structure and method for Cu/ultra low k integration Dec. 7, 2010
7842193 Polishing liquid Nov. 30, 2010
7829357 Method and test structure for monitoring CMP processes in metallization layers of semiconductor devices Nov. 9, 2010
RE41842 Methods of forming electrical interconnects on integrated circuit substrates using selective slurries Oct. 19, 2010
7790609 Method of forming metal line in semiconductor device Sep. 7, 2010
7781329 Reducing leakage in dielectric materials including metal regions including a metal cap layer in semiconductor devices Aug. 24, 2010
7771779 Planarized microelectronic substrates Aug. 10, 2010
7737029 Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby Jun. 15, 2010
7718545 Fabrication process May. 18, 2010
7704856 Semiconductor device, wiring substrate forming method, and substrate processing apparatus Apr. 27, 2010
7655563 Method for preventing the formation of dentrites in a semiconductor Feb. 2, 2010
7601636 Implementation of a metal barrier in an integrated electronic circuit Oct. 13, 2009
7572662 Method of fabricating phase change RAM including a fullerene layer Aug. 11, 2009
7534719 Method for reduction in metal dishing after CMP May. 19, 2009
7528066 Structure and method for metal integration May. 5, 2009

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