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Class Information
Number: 438/639
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > With formation of opening (i.e., viahole) in insulative layer > Having viahole with sidewall component
Description: Processes wherein the viahole has an additional component formed along the sidewall thereof.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7618889 |
Dual damascene fabrication with low k materials |
Nov. 17, 2009 |
| 7615485 |
Method of manufacture of contact plug and interconnection layer of semiconductor device |
Nov. 10, 2009 |
| 7608536 |
Method of manufacturing contact opening |
Oct. 27, 2009 |
| 7598616 |
Interconnect structure |
Oct. 6, 2009 |
| 7589024 |
Process for producing semiconductor integrated circuit device |
Sep. 15, 2009 |
| 7589014 |
Semiconductor device having multiple wiring layers and method of producing the same |
Sep. 15, 2009 |
| 7585766 |
Methods of manufacturing copper interconnect systems |
Sep. 8, 2009 |
| 7575995 |
Method of forming fine metal pattern and method of forming metal line using the same |
Aug. 18, 2009 |
| 7576001 |
Manufacturing method for semiconductor device |
Aug. 18, 2009 |
| 7572729 |
Method of manufacturing semiconductor device |
Aug. 11, 2009 |
| 7572727 |
Semiconductor formation method that utilizes multiple etch stop layers |
Aug. 11, 2009 |
| 7569453 |
Contact structure |
Aug. 4, 2009 |
| 7560375 |
Gas dielectric structure forming methods |
Jul. 14, 2009 |
| 7550379 |
Alignment mark, use of a hard mask material, and method |
Jun. 23, 2009 |
| 7544605 |
Method of making a contact on a backside of a die |
Jun. 9, 2009 |
| 7544608 |
Porous and dense hybrid interconnect structure and method of manufacture |
Jun. 9, 2009 |
| 7538028 |
Barrier layer, IC via, and IC line forming methods |
May. 26, 2009 |
| 7538037 |
Method for manufacturing semiconductor device |
May. 26, 2009 |
| 7534722 |
Back-to-front via process |
May. 19, 2009 |
| 7531450 |
Method of fabricating semiconductor device having contact hole with high aspect-ratio |
May. 12, 2009 |
| 7528493 |
Interconnect structure and method of fabrication of same |
May. 5, 2009 |
| 7524756 |
Process of forming a semiconductor assembly having a contact structure and contact liner |
Apr. 28, 2009 |
| 7521348 |
Method of fabricating semiconductor device having fine contact holes |
Apr. 21, 2009 |
| 7517736 |
Structure and method of chemically formed anchored metallic vias |
Apr. 14, 2009 |
| 7510959 |
Method of manufacturing a semiconductor device having damascene structures with air gaps |
Mar. 31, 2009 |
| 7510965 |
Method for fabricating a dual damascene structure |
Mar. 31, 2009 |
| 7504334 |
Semiconductor device and method for manufacturing same |
Mar. 17, 2009 |
| 7504287 |
Methods for fabricating an integrated circuit |
Mar. 17, 2009 |
| 7498254 |
Plating seed layer including an oxygen/nitrogen transition region for barrier enhancement |
Mar. 3, 2009 |
| 7494922 |
Small electrode for phase change memories |
Feb. 24, 2009 |
| 7491641 |
Method of forming a conductive line and a method of forming a conductive contact adjacent to and insulated from a conductive line |
Feb. 17, 2009 |
| 7485578 |
Semiconductor device |
Feb. 3, 2009 |
| 7485587 |
Method of making a semiconductor device having improved contacts |
Feb. 3, 2009 |
| 7482694 |
Semiconductor device and its manufacturing method |
Jan. 27, 2009 |
| 7476610 |
Removable spacer |
Jan. 13, 2009 |
| 7476614 |
Method of fabricating semiconductor device |
Jan. 13, 2009 |
| 7473636 |
Method to improve time dependent dielectric breakdown |
Jan. 6, 2009 |
| 7470989 |
Technique for perfecting the active regions of wide bandgap semiconductor nitride devices |
Dec. 30, 2008 |
| 7459384 |
Preventing cavitation in high aspect ratio dielectric regions of semiconductor device |
Dec. 2, 2008 |
| 7453141 |
Semiconductor device package, method of manufacturing the same, and semiconductor device |
Nov. 18, 2008 |
| 7446047 |
Metal structure with sidewall passivation and method |
Nov. 4, 2008 |
| 7439144 |
CMOS gate structures fabricated by selective oxidation |
Oct. 21, 2008 |
| 7435673 |
Methods of forming integrated circuit devices having metal interconnect structures therein |
Oct. 14, 2008 |
| 7435676 |
Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity |
Oct. 14, 2008 |
| 7435679 |
Alloyed underlayer for microelectronic interconnects |
Oct. 14, 2008 |
| 7410892 |
Methods of fabricating integrated circuit devices having self-aligned contact structures |
Aug. 12, 2008 |
| 7402514 |
Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer |
Jul. 22, 2008 |
| 7402515 |
Method of forming through-silicon vias with stress buffer collars and resulting devices |
Jul. 22, 2008 |
| 7396762 |
Interconnect structures with linear repair layers and methods for forming such interconnection structures |
Jul. 8, 2008 |
| 7393779 |
Shrinking contact apertures through LPD oxide |
Jul. 1, 2008 |
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