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Class Information
Number: 438/638
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > With formation of opening (i.e., viahole) in insulative layer > Having viaholes of diverse width
Description: Processes wherein at least one viahole is formed which is wider than at least one other viahole.










Patents under this class:

Patent Number Title Of Patent Date Issued
8709942 Methods for fabricating semiconductor devices Apr. 29, 2014
8709937 Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same Apr. 29, 2014
8709936 Method and structure of forming backside through silicon via connections Apr. 29, 2014
8703605 High yield and high throughput method for the manufacture of integrated circuit devices of improved integrity, performance and reliability Apr. 22, 2014
8703604 Creation of vias and trenches with different depths Apr. 22, 2014
8703603 Device package and methods for the fabrication and testing thereof Apr. 22, 2014
8692288 Heterojunction bipolar transistors and methods of manufacture Apr. 8, 2014
8685853 Dual damascene copper process using a selected mask Apr. 1, 2014
8673772 Biosensor chip and a method of manufacturing the same Mar. 18, 2014
8669175 Semiconductor device and manufacturing of the semiconductor device Mar. 11, 2014
8664759 Integrated circuit with heat conducting structures for localized thermal control Mar. 4, 2014
8664108 Stacked multilayer structure and manufacturing method thereof Mar. 4, 2014
8647991 Method for forming dual damascene opening Feb. 11, 2014
8640072 Method for forming an electrical connection between metal layers Jan. 28, 2014
8633113 Method for fabricating a bottom oxide layer in a trench Jan. 21, 2014
8629058 Methods for via structure with improved reliability Jan. 14, 2014
8629057 Semiconductor substrates with unitary vias and via terminals, and associated systems and methods Jan. 14, 2014
8617983 Local interconnect having increased misalignment tolerance Dec. 31, 2013
8610275 Semiconductor contact structure including a spacer formed within a via and method of manufacturing the same Dec. 17, 2013
8592990 Semiconductor device and method of manufacturing semiconductor device Nov. 26, 2013
8592989 Integrated circuit package system with bump over via Nov. 26, 2013
8592979 Semiconductor device conductive pattern structures and methods of manufacturing the same Nov. 26, 2013
8592691 Printed wiring board Nov. 26, 2013
8592297 Wafer and method of processing wafer Nov. 26, 2013
8587131 Through-silicon via and fabrication method thereof Nov. 19, 2013
8569167 Methods for forming a semiconductor structure Oct. 29, 2013
8569166 Methods of modifying interlayer adhesion Oct. 29, 2013
8563426 Shrinkage of contact elements and vias in a semiconductor device by incorporating additional tapering material Oct. 22, 2013
8563389 Integrated circuit having silicon resistor and method of forming the same Oct. 22, 2013
8531037 Semiconductor chip having power supply line with minimized voltage drop Sep. 10, 2013
8519538 Laser etch via formation Aug. 27, 2013
8518821 Semiconductor device and a method of manufacturing the same Aug. 27, 2013
8513815 Implementing integrated circuit mixed double density and high performance wire structure Aug. 20, 2013
8513113 Methods of forming semiconductor constructions and assemblies Aug. 20, 2013
8501618 Semiconductor device and method of forming RDL wider than contact pad along first axis and narrower than contact pad along second axis Aug. 6, 2013
8497204 Method for reducing dielectric overetch when making contact to conductive features Jul. 30, 2013
8492271 Semiconductor device and method of manufacturing the same Jul. 23, 2013
8492269 Hybrid contact structure with low aspect ratio contacts in a semiconductor device Jul. 23, 2013
8492267 Pillar interconnect chip to package and global wiring structure Jul. 23, 2013
8488128 Line edge roughness measuring technique and test structure Jul. 16, 2013
8487412 Semiconductor device and a method of manufacturing the same Jul. 16, 2013
8461678 Structure with self aligned resist layer on an interconnect surface and method of making same Jun. 11, 2013
8455357 Method of plating through wafer vias in a wafer for 3D packaging Jun. 4, 2013
8455351 Method of forming an integrated circuit interconnect structure Jun. 4, 2013
8455350 Integrated circuit system employing gate shield and/or ground shield Jun. 4, 2013
8455348 Manufacturing method of semiconductor device Jun. 4, 2013
8450206 Method of forming a semiconductor device including a stress buffer material formed above a low-k metallization system May. 28, 2013
8440916 Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method May. 14, 2013
8435802 Conductor layout technique to reduce stress-induced void formations May. 7, 2013
8420528 Manufacturing method of a semiconductor device having wirings Apr. 16, 2013











 
 
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