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Class Information
Number: 438/637
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > With formation of opening (i.e., viahole) in insulative layer
Description: Processes including a step of forming an opening in the separating insulating layer.










Sub-classes under this class:

Class Number Class Name Patents
438/640 Having viahole of tapered shape 576
438/639 Having viahole with sidewall component 856
438/638 Having viaholes of diverse width 1,183


Patents under this class:

Patent Number Title Of Patent Date Issued
8710672 Semiconductor device and method of manufacturing the same Apr. 29, 2014
8710648 Wafer level packaging structure with large contact area and preparation method thereof Apr. 29, 2014
8709942 Methods for fabricating semiconductor devices Apr. 29, 2014
8704377 Compliant conductive nano-particle electrical interconnect Apr. 22, 2014
8704373 Semiconductor device and a method of manufacturing the same Apr. 22, 2014
8704343 Borderless interconnect line structure self-aligned to upper and lower level contact vias Apr. 22, 2014
8704284 Semiconductor device having bit line expanding islands Apr. 22, 2014
8703609 Through-substrate via for semiconductor device Apr. 22, 2014
8703605 High yield and high throughput method for the manufacture of integrated circuit devices of improved integrity, performance and reliability Apr. 22, 2014
8703604 Creation of vias and trenches with different depths Apr. 22, 2014
8703603 Device package and methods for the fabrication and testing thereof Apr. 22, 2014
8692364 Semiconductor device and method for manufacturing the same Apr. 8, 2014
8692288 Heterojunction bipolar transistors and methods of manufacture Apr. 8, 2014
8691664 Backside process for a substrate Apr. 8, 2014
8686568 Semiconductor package substrates having layered circuit segments, and related methods Apr. 1, 2014
8685860 Semiconductor structure and manufacturing method thereof Apr. 1, 2014
8685853 Dual damascene copper process using a selected mask Apr. 1, 2014
8685851 MOS device with memory function and manufacturing method thereof Apr. 1, 2014
8685793 Chip assembly having via interconnects joined by plating Apr. 1, 2014
8682466 Automatic virtual metrology for semiconductor wafer result prediction Mar. 25, 2014
8674508 Seal ring structures with reduced moisture-induced reliability degradation Mar. 18, 2014
8673779 Interconnect with self-formed barrier Mar. 18, 2014
8673775 Methods of forming semiconductor structures Mar. 18, 2014
8673771 Pattern forming method Mar. 18, 2014
8673770 Methods of forming conductive structures in dielectric layers on an integrated circuit device Mar. 18, 2014
8673769 Methods and apparatuses for three dimensional integrated circuits Mar. 18, 2014
8673767 Manufacturing method for semiconductor device Mar. 18, 2014
8673766 Methods of forming copper-based conductive structures by forming a copper-based seed layer having an as-deposited thickness profile and thereafter performing an etching process and electroless Mar. 18, 2014
8673764 Method and system for making and cleaning semiconductor device Mar. 18, 2014
8669655 Chip package and a method for manufacturing a chip package Mar. 11, 2014
8669180 Semiconductor device with self aligned end-to-end conductive line structure and method of forming the same Mar. 11, 2014
8664759 Integrated circuit with heat conducting structures for localized thermal control Mar. 4, 2014
8664114 Image sensor and method for fabricating the same Mar. 4, 2014
8664113 Multilayer interconnect structure and method for integrated circuits Mar. 4, 2014
8664112 Methods for forming interconnect structures for integration of multi-layered integrated circuit devices Mar. 4, 2014
8664108 Stacked multilayer structure and manufacturing method thereof Mar. 4, 2014
8664090 Electronic component package fabrication method Mar. 4, 2014
8664044 Method of fabricating land grid array semiconductor package Mar. 4, 2014
8652966 Semiconductor device manufacturing method and semiconductor device Feb. 18, 2014
8647991 Method for forming dual damascene opening Feb. 11, 2014
8647982 Methods of forming interconnects in a semiconductor structure Feb. 11, 2014
8647979 Buffer layer to enhance photo and/or laser sintering Feb. 11, 2014
8644063 Fabrication and integration of devices with top and bottom electrodes including magnetic tunnel junctions Feb. 4, 2014
8643191 On-chip radial cavity power divider/combiner Feb. 4, 2014
8642384 Semiconductor device and method of forming non-linear interconnect layer with extended length for joint reliability Feb. 4, 2014
8640072 Method for forming an electrical connection between metal layers Jan. 28, 2014
8637403 Locally tailoring chemical mechanical polishing (CMP) polish rate for dielectrics Jan. 28, 2014
8637389 Resist feature and removable spacer pitch doubling patterning method for pillar structures Jan. 28, 2014
8633113 Method for fabricating a bottom oxide layer in a trench Jan. 21, 2014
8633104 Methods of manufacturing three-dimensional semiconductor devices Jan. 21, 2014











 
 
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