| |
 |
|
Class Information
Number: 438/637
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > With formation of opening (i.e., viahole) in insulative layer
Description: Processes including a step of forming an opening in the separating insulating layer.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| RE40983 |
Method to plate C4 to copper stud |
Nov. 17, 2009 |
| 7618889 |
Dual damascene fabrication with low k materials |
Nov. 17, 2009 |
| 7615486 |
Apparatus and method for integrated surface treatment and deposition for copper interconnect |
Nov. 10, 2009 |
| 7615485 |
Method of manufacture of contact plug and interconnection layer of semiconductor device |
Nov. 10, 2009 |
| 7615484 |
Integrated circuit manufacturing method using hard mask |
Nov. 10, 2009 |
| 7615483 |
Printed metal mask for UV, e-beam, ion-beam and X-ray patterning |
Nov. 10, 2009 |
| 7615480 |
Methods of post-contact back end of the line through-hole via integration |
Nov. 10, 2009 |
| 7611986 |
Dual damascene patterning method |
Nov. 3, 2009 |
| 7611985 |
Formation of holes in substrates using dewetting coatings |
Nov. 3, 2009 |
| 7611983 |
Semiconductor device and a manufacturing method of the same |
Nov. 3, 2009 |
| 7611982 |
Method of forming sheet having foreign material portions used for forming multi-layer wiring board and sheet having foreign portions |
Nov. 3, 2009 |
| 7608534 |
Interconnection of through-wafer vias using bridge structures |
Oct. 27, 2009 |
| 7605085 |
Method of manufacturing interconnecting structure with vias |
Oct. 20, 2009 |
| 7605076 |
Method of manufacturing a semiconductor device from which damage layers and native oxide films in connection holes have been removed |
Oct. 20, 2009 |
| 7605075 |
Multilayer circuit board and method of manufacturing the same |
Oct. 20, 2009 |
| 7605066 |
Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components |
Oct. 20, 2009 |
| 7602047 |
Semiconductor device having through vias |
Oct. 13, 2009 |
| 7601634 |
Process for producing a contact pad on a region of an integrated circuit, in particular on the electrodes of a transistor |
Oct. 13, 2009 |
| 7601630 |
Semiconductor device and method for fabricating the same |
Oct. 13, 2009 |
| 7601624 |
Device comprising an ohmic via contact, and method of fabricating thereof |
Oct. 13, 2009 |
| 7601607 |
Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects |
Oct. 13, 2009 |
| 7598616 |
Interconnect structure |
Oct. 6, 2009 |
| 7598174 |
Feature patterning methods |
Oct. 6, 2009 |
| 7598171 |
Method of manufacturing a semiconductor device |
Oct. 6, 2009 |
| 7598169 |
Method to remove beol sacrificial materials and chemical residues by irradiation |
Oct. 6, 2009 |
| 7598168 |
Method of fabricating dual damascene interconnection and etchant for stripping sacrificial layer |
Oct. 6, 2009 |
| 7598167 |
Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures |
Oct. 6, 2009 |
| 7598165 |
Methods for forming a multiplexer of a memory device |
Oct. 6, 2009 |
| 7595556 |
Semiconductor device and method for manufacturing the same |
Sep. 29, 2009 |
| 7595529 |
Semiconductor integrated circuit devices having upper pattern aligned with lower pattern molded by semiconductor substrate and methods of forming the same |
Sep. 29, 2009 |
| 7595269 |
Semiconductor device comprising a copper alloy as a barrier layer in a copper metallization layer |
Sep. 29, 2009 |
| 7595254 |
Method of manufacturing a semiconductor device |
Sep. 29, 2009 |
| 7592253 |
Method for forming a damascene pattern of a copper metallization layer |
Sep. 22, 2009 |
| 7592252 |
Versatile system for charge dissipation in the formation of semiconductor device structures |
Sep. 22, 2009 |
| 7592251 |
Hafnium tantalum titanium oxide films |
Sep. 22, 2009 |
| 7592247 |
Sub-lithographic local interconnects, and methods for forming same |
Sep. 22, 2009 |
| 7589021 |
Copper metal interconnection with a local barrier metal layer |
Sep. 15, 2009 |
| 7589016 |
Method of depositing a sculptured copper seed layer |
Sep. 15, 2009 |
| 7589014 |
Semiconductor device having multiple wiring layers and method of producing the same |
Sep. 15, 2009 |
| 7589013 |
Electrode structure and method of manufacturing the same, phase-change memory device having the electrode structure and method of manufacturing the same |
Sep. 15, 2009 |
| 7589011 |
Semiconductor device and method of forming intermetal dielectric layer |
Sep. 15, 2009 |
| 7589008 |
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
Sep. 15, 2009 |
| 7585765 |
Formation of oxidation-resistant seed layer for interconnect applications |
Sep. 8, 2009 |
| 7585764 |
VIA bottom contact and method of manufacturing same |
Sep. 8, 2009 |
| 7582564 |
Process and composition for conductive material removal by electrochemical mechanical polishing |
Sep. 1, 2009 |
| 7582560 |
Method for fabricating semiconductor device |
Sep. 1, 2009 |
| 7582559 |
Method of manufacturing a semiconductor device having voids in a polysilicon layer |
Sep. 1, 2009 |
| 7582557 |
Process for low resistance metal cap |
Sep. 1, 2009 |
| 7582556 |
Circuitry component and method for forming the same |
Sep. 1, 2009 |
| 7579278 |
Topography directed patterning |
Aug. 25, 2009 |
|
|
|
