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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.

Patents under this class:
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Patent Number Title Of Patent Date Issued
6500755 Resist trim process to define small openings in dielectric layers Dec. 31, 2002
6500754 Anneal hillock suppression method in integrated circuit interconnects Dec. 31, 2002
6498098 Method of forming embedded wiring in a groove in an insulating layer Dec. 24, 2002
6492268 Method of forming a copper wiring in a semiconductor device Dec. 10, 2002
6492260 Method of fabricating damascene metal wiring Dec. 10, 2002
6489240 Method for forming copper interconnects Dec. 3, 2002
6486066 Method of generating integrated circuit feature layout for improved chemical mechanical polishing Nov. 26, 2002
6486057 Process for preparing Cu damascene interconnection Nov. 26, 2002
6482733 Protective layers prior to alternating layer deposition Nov. 19, 2002
6482743 Method of forming a semiconductor device using CMP to polish a metal film Nov. 19, 2002
6480017 Evaluating pattern for measuring an erosion of a semiconductor wafer polished by a chemical mechanical polishing Nov. 12, 2002
6479380 Semiconductor device and manufacturing method thereof Nov. 12, 2002
6475810 Method of manufacturing embedded organic stop layer for dual damascene patterning Nov. 5, 2002
6475900 Method for manufacturing a metal interconnection having enhanced filling capability Nov. 5, 2002
6475914 Method of manufacturing semiconductor device for protecting Cu layer from post chemical mechanical polishing-corrosion Nov. 5, 2002
6472304 Wire bonding to copper Oct. 29, 2002
6472312 Methods for inhibiting microelectronic damascene processing induced low dielectric constant dielectric layer physical degradation Oct. 29, 2002
6472313 Device formation method for preventing pattern shift caused by glass layer reflow Oct. 29, 2002
6472306 Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer Oct. 29, 2002
6472314 Diamond barrier layer Oct. 29, 2002
6468906 Passivation of copper interconnect surfaces with a passivating metal layer Oct. 22, 2002
6468895 Pattern forming method Oct. 22, 2002
6465339 Technique for intralevel capacitive isolation of interconnect paths Oct. 15, 2002
6465354 Method of improving the planarization of wiring by CMP Oct. 15, 2002
RE37865 Semiconductor electrical interconnection methods Oct. 1, 2002
6458689 Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish Oct. 1, 2002
6458690 Method for manufacturing a multilayer interconnection structure Oct. 1, 2002
6455425 Selective deposition process for passivating top interface of damascene-type Cu interconnect lines Sep. 24, 2002
6455434 Prevention of slurry build-up within wafer topography during polishing Sep. 24, 2002
6444573 Method of making a slot via filled dual damascene structure with a middle stop layer Sep. 3, 2002
6444569 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process Sep. 3, 2002
6444567 Process for alloying damascene-type Cu interconnect lines Sep. 3, 2002
6444405 Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductors substrate Sep. 3, 2002
6440842 Method of forming a dual damascene structure by patterning a sacrificial layer to define the plug portions of the structure Aug. 27, 2002
6436811 Method of forming a copper-containing metal interconnect using a chemical mechanical planarization (CMP) slurry Aug. 20, 2002
6436810 Bi-layer resist process for dual damascene Aug. 20, 2002
6432770 Semiconductor arrangement having capacitive structure and manufacture thereof Aug. 13, 2002
6432811 Method of forming structural reinforcement of highly porous low k dielectric films by Cu diffusion barrier structures Aug. 13, 2002
6429105 Method of manufacturing semiconductor device Aug. 6, 2002
6429118 Elimination of electrochemical deposition copper line damage for damascene processing Aug. 6, 2002
6429119 Dual damascene process to reduce etch barrier thickness Aug. 6, 2002
6429129 Method of using silicon rich carbide as a barrier material for fluorinated materials Aug. 6, 2002
6426297 Differential pressure chemical-mechanical polishing in integrated circuit interconnects Jul. 30, 2002
6419554 Fixed abrasive chemical-mechanical planarization of titanium nitride Jul. 16, 2002
6420261 Semiconductor device manufacturing method Jul. 16, 2002
6420269 Cerium oxide abrasive for polishing insulating films formed on substrate and methods for using the same Jul. 16, 2002
6420259 Formation of a self-aligned structure Jul. 16, 2002
6420258 Selective growth of copper for advanced metallization Jul. 16, 2002
RE37786 Copper-based metal polishing solution and method for manufacturing semiconductor device Jul. 9, 2002
6417095 Method for fabricating a dual damascene structure Jul. 9, 2002

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