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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6617233 Process of fabricating an anti-fuse for avoiding a key hole exposed Sep. 9, 2003
6617241 Method of thick film planarization Sep. 9, 2003
6613646 Methods for reduced trench isolation step height Sep. 2, 2003
6602779 Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer Aug. 5, 2003
6599830 Semiconductor device and manufacturing method thereof Jul. 29, 2003
6596639 Method for chemical/mechanical planarization of a semiconductor wafer having dissimilar metal pattern densities Jul. 22, 2003
6596624 Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a chip carrier Jul. 22, 2003
6596629 Method for forming wire in semiconductor device Jul. 22, 2003
6596625 Method and device for producing a metal/metal contact in a multilayer metallization of an integrated circuit Jul. 22, 2003
6596627 Very low dielectric constant plasma-enhanced CVD films Jul. 22, 2003
6593228 Method of fabricating a patterned metal-containing layer on a semiconductor wafer Jul. 15, 2003
6582579 Methods for repairing defects on a semiconductor substrate Jun. 24, 2003
6576553 Chemical mechanical planarization of conductive material Jun. 10, 2003
6573173 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process Jun. 3, 2003
6573606 Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect Jun. 3, 2003
6569760 Method to prevent poison via May. 27, 2003
6559044 Method for forming contacts May. 6, 2003
6559045 Fabrication of integrated circuits with borderless vias May. 6, 2003
6555467 Method of making air gaps copper interconnect Apr. 29, 2003
6551922 Method for making a semiconductor device by variable chemical mechanical polish downforce Apr. 22, 2003
6551921 Method of polishing a stack of dielectric layers including a fluorine containing silicon oxide layer Apr. 22, 2003
6551934 Process for fabricating semiconductor device and apparatus for fabricating semiconductor device Apr. 22, 2003
6551920 Semiconductor device and fabrication method thereof Apr. 22, 2003
6551915 Thermal annealing/hydrogen containing plasma method for forming structurally stable low contact resistance damascene conductor structure Apr. 22, 2003
6548399 Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer Apr. 15, 2003
6544891 Method to eliminate post-CMP copper flake defect Apr. 8, 2003
6541372 Method for manufacturing a conductor structure for an integrated circuit Apr. 1, 2003
6541367 Very low dielectric constant plasma-enhanced CVD films Apr. 1, 2003
RE38049 Optimized container stacked capacitor dram cell utilizing sacrificial oxide deposition and chemical mechanical polishing Mar. 25, 2003
6537913 Method of making a semiconductor device with aluminum capped copper interconnect pads Mar. 25, 2003
6534389 Dual level contacts and method for forming Mar. 18, 2003
6534397 Pre-treatment of low-k dielectric for prevention of photoresist poisoning Mar. 18, 2003
6531353 Method for fabricating semiconductor device Mar. 11, 2003
6531387 Polishing of conductive layers in fabrication of integrated circuits Mar. 11, 2003
6530995 Processing compositions and methods of using same Mar. 11, 2003
6528419 Process of fabricating an integrated circuit Mar. 4, 2003
6521922 Passivation film on a semiconductor wafer Feb. 18, 2003
6521524 Via filled dual damascene structure with middle stop layer and method for making the same Feb. 18, 2003
6521523 Method for forming selective protection layers on copper interconnects Feb. 18, 2003
6518185 Integration scheme for non-feature-size dependent cu-alloy introduction Feb. 11, 2003
6518157 Methods of planarizing insulating layers on regions having different etching rates Feb. 11, 2003
6514852 Semiconductor device and method of manufacturing the same Feb. 4, 2003
6514861 Manufacturing a semiconductor wafer according to the process time by process tool Feb. 4, 2003
6514844 Sidewall treatment for low dielectric constant (low K) materials by ion implantation Feb. 4, 2003
6511906 Selective CMP scheme Jan. 28, 2003
6511907 Method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process Jan. 28, 2003
6509262 Method of reducing electromigration in copper lines by calcium-doping copper surfaces in a chemical solution Jan. 21, 2003
6503828 Process for selective polishing of metal-filled trenches of integrated circuit structures Jan. 7, 2003
6503827 Method of reducing planarization defects Jan. 7, 2003
6503834 Process to increase reliability CuBEOL structures Jan. 7, 2003

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