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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6739953 Mechanical stress free processing method May. 25, 2004
6737347 Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device May. 18, 2004
6737349 Method of forming a copper wiring in a semiconductor device May. 18, 2004
6737348 Method for forming buried interconnect May. 18, 2004
6734103 Method of polishing a semiconductor device May. 11, 2004
6734097 Liner with poor step coverage to improve contact resistance in W contacts May. 11, 2004
6730592 Methods for planarization of metal-containing surfaces using halogens and halide salts May. 4, 2004
6730590 Semiconductor integrated circuit device and fabrication process thereof May. 4, 2004
6727172 Process to reduce chemical mechanical polishing damage of narrow copper lines Apr. 27, 2004
6723626 Method of manufacturing semiconductor device Apr. 20, 2004
6720250 Method of manufacturing a semiconductor device using a slurry for chemical mechanical polishing of copper Apr. 13, 2004
6720249 Protective hardmask for producing interconnect structures Apr. 13, 2004
6716741 Method of patterning dielectric layer with low dielectric constant Apr. 6, 2004
6716771 Method for post-CMP conversion of a hydrophobic surface of a low-k dielectric layer to a hydrophilic surface Apr. 6, 2004
6716743 Method of manufacturing a semiconductor device Apr. 6, 2004
6713385 Implanting ions in shallow trench isolation structures Mar. 30, 2004
6713386 Method of preventing resist poisoning in dual damascene structures Mar. 30, 2004
6709974 Method of preventing seam defects in isolated lines Mar. 23, 2004
6709973 Method of fabricating semiconductor device Mar. 23, 2004
6706633 Method of forming a self-aligned contact pad for use in a semiconductor device Mar. 16, 2004
6699783 Method for controlling conformality with alternating layer deposition Mar. 2, 2004
6696361 Post-CMP removal of surface contaminants from silicon wafer Feb. 24, 2004
6696357 Method for manufacturing semiconductor integrated circuit devices using a conductive layer to prevent peeling between a bonding pad and an underlying insulating film Feb. 24, 2004
6692580 Method of cleaning a dual damascene structure Feb. 17, 2004
6689681 Semiconductor device and a method of manufacturing the same Feb. 10, 2004
6686285 Semiconductor device manufacture method preventing dishing and erosion during chemical mechanical polishing Feb. 3, 2004
6686271 Protective layers prior to alternating layer deposition Feb. 3, 2004
6686270 Dual damascene trench depth monitoring Feb. 3, 2004
6673712 Method of forming dual-implanted gate and structure formed by the same Jan. 6, 2004
6670272 Method for reducing dishing in chemical mechanical polishing Dec. 30, 2003
6670274 Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure Dec. 30, 2003
6667239 Chemical mechanical polishing of copper-oxide damascene structures Dec. 23, 2003
6664178 Method of forming buried interconnecting wire Dec. 16, 2003
6660634 Method of forming reliable capped copper interconnects Dec. 9, 2003
6660638 CMP process leaving no residual oxide layer or slurry particles Dec. 9, 2003
6656834 Method of selectively alloying interconnect regions by deposition process Dec. 2, 2003
6653227 Method of cobalt silicidation using an oxide-Titanium interlayer Nov. 25, 2003
6653224 Methods for fabricating interconnect structures having Low K dielectric properties Nov. 25, 2003
6649523 Method and system to provide material removal and planarization employing a reactive pad Nov. 18, 2003
6642139 Method for forming interconnection structure in an integration circuit Nov. 4, 2003
6638853 Method for avoiding photoresist resist residue on semioconductor feature sidewalls Oct. 28, 2003
6638854 Semiconductor device and method for manufacturing the same Oct. 28, 2003
6635562 Methods and solutions for cleaning polished aluminum-containing layers Oct. 21, 2003
6633084 Semiconductor wafer for improved chemical-mechanical polishing over large area features Oct. 14, 2003
6627546 Process for removing contaminant from a surface and composition useful therefor Sep. 30, 2003
6627926 Method of designing and structure for visual and electrical test of semiconductor devices Sep. 30, 2003
6627553 Composition for removing side wall and method of removing side wall Sep. 30, 2003
6624065 Method of fabricating a semiconductor device using a damascene metal gate Sep. 23, 2003
6620725 Reduction of Cu line damage by two-step CMP Sep. 16, 2003
6620726 Method of forming metal lines having improved uniformity on a substrate Sep. 16, 2003

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