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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Patent Number Title Of Patent Date Issued
7229915 Method for manufacturing semiconductor device Jun. 12, 2007
7223685 Damascene fabrication with electrochemical layer removal May. 29, 2007
7217653 Interconnects forming method and interconnects forming apparatus May. 15, 2007
7214602 Method of forming a conductive structure May. 8, 2007
7211508 Atomic layer deposition of tantalum based barrier materials May. 1, 2007
7208404 Method to reduce Rs pattern dependence effect Apr. 24, 2007
7208406 Method for forming gate in semiconductor device Apr. 24, 2007
7205225 Method of manufacturing a semiconductor device and semiconductor device obtained by using such a method Apr. 17, 2007
7202161 Substrate processing method and apparatus Apr. 10, 2007
7199045 Metal-filled openings for submicron devices and methods of manufacture thereof Apr. 3, 2007
7199043 Method of forming copper wiring in semiconductor device Apr. 3, 2007
7189650 Method and apparatus for copper film quality enhancement with two-step deposition Mar. 13, 2007
7186574 CMP process metrology test structures Mar. 6, 2007
7183199 Method of reducing the pattern effect in the CMP process Feb. 27, 2007
7172963 Manufacturing method of semiconductor integrated circuit device that includes chemically and mechanically polishing two conductive layers using two polishing pads that have different propertie Feb. 6, 2007
7172962 Method of manufacturing a semiconductor device Feb. 6, 2007
7172908 Magnetic memory cells and manufacturing methods Feb. 6, 2007
7169701 Dual damascene trench formation to avoid low-K dielectric damage Jan. 30, 2007
7153706 Ferroelectric capacitor having a substantially planar dielectric layer and a method of manufacture therefor Dec. 26, 2006
7153767 Chemical mechanical polishing stopper film, process for producing the same, and method of chemical mechanical polishing Dec. 26, 2006
7144808 Integration flow to prevent delamination from copper Dec. 5, 2006
7132363 Stabilizing fluorine etching of low-k materials Nov. 7, 2006
7122465 Method for achieving increased control over interconnect line thickness across a wafer and between wafers Oct. 17, 2006
7115510 Method for electrochemically processing a workpiece Oct. 3, 2006
7104869 Barrier removal at low polish pressure Sep. 12, 2006
7101786 Method for forming a metal line in a semiconductor device Sep. 5, 2006
7098129 Interlayer insulation film used for multilayer interconnect of semiconductor integrated circuit and method of manufacturing the same Aug. 29, 2006
7098130 Method of forming dual damascene structure Aug. 29, 2006
7091123 Method of forming metal wiring line including using a first insulating film as a stopper film Aug. 15, 2006
7087518 Method of passivating and/or removing contaminants on a low-k dielectric/copper surface Aug. 8, 2006
7084055 Method for manufacturing semiconductor integrated circuit device Aug. 1, 2006
7074710 Method of wafer patterning for reducing edge exclusion zone Jul. 11, 2006
7071099 Forming of local and global wiring for semiconductor product Jul. 4, 2006
7071074 Structure and method for placement, sizing and shaping of dummy structures Jul. 4, 2006
7067416 Method of forming a conductive contact Jun. 27, 2006
RE39126 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs Jun. 13, 2006
7060606 Method and apparatus for chemical mechanical polishing of semiconductor substrates Jun. 13, 2006
7052952 Method for forming wire line by damascene process using hard mask formed from contacts May. 30, 2006
7052995 Process of manufacturing semiconductor device including chemical-mechanical polishing May. 30, 2006
7045454 Chemical mechanical planarization of conductive material May. 16, 2006
7045453 Very low effective dielectric constant interconnect structures and methods for fabricating the same May. 16, 2006
7041592 Method for forming a metal interconnection layer of a semiconductor device using a modified dual damascene process May. 9, 2006
7037822 Method of forming metal line in semiconductor device May. 2, 2006
7037836 Method of manufacturing a semiconductor device without oxidized copper layer May. 2, 2006
7012335 Semiconductor device wiring and method of manufacturing the same Mar. 14, 2006
7012021 Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device Mar. 14, 2006
7010381 Versatile system for controlling semiconductor topography Mar. 7, 2006
6995085 Underlayer protection for the dual damascene etching Feb. 7, 2006
6995090 Polishing slurry for use in CMP of SiC series compound, polishing method, and method of manufacturing semiconductor device Feb. 7, 2006
6992002 Shapes-based migration of aluminum designs to copper damascence Jan. 31, 2006

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