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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.










Patents under this class:
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Patent Number Title Of Patent Date Issued
7544606 Method to implement stress free polishing Jun. 9, 2009
7541225 Method of manufacturing a thin film transistor array panel that includes using chemical mechanical polishing of a conductive film to form a pixel electrode connected to a drain electrode Jun. 2, 2009
7541279 Method for manufacturing semiconductor device Jun. 2, 2009
7538037 Method for manufacturing semiconductor device May. 26, 2009
7534719 Method for reduction in metal dishing after CMP May. 19, 2009
7531447 Process for forming integrated circuit comprising copper lines May. 12, 2009
7528059 Method for reducing polish-induced damage in a contact structure by forming a capping layer May. 5, 2009
7524752 Method of manufacturing semiconductor device Apr. 28, 2009
7521348 Method of fabricating semiconductor device having fine contact holes Apr. 21, 2009
7510972 Method of processing substrate, post-chemical mechanical polishing cleaning method, and method of and program for manufacturing electronic device Mar. 31, 2009
7507657 Method for fabricating storage node contact in semiconductor device Mar. 24, 2009
7504287 Methods for fabricating an integrated circuit Mar. 17, 2009
7494921 Aluminum metal line of a semiconductor device and method of fabricating the same Feb. 24, 2009
7479433 Method for manufacturing semiconductor device Jan. 20, 2009
7470612 Method of forming metal wiring layer of semiconductor device Dec. 30, 2008
7470630 Approach to reduce parasitic capacitance from dummy fill Dec. 30, 2008
7465977 Method for producing a packaged integrated circuit Dec. 16, 2008
7465652 Method of forming a catalyst layer on the barrier layer of a conductive interconnect of a semiconductor device Dec. 16, 2008
7453152 Device having reduced chemical mechanical planarization Nov. 18, 2008
7435673 Methods of forming integrated circuit devices having metal interconnect structures therein Oct. 14, 2008
7432191 Method of forming a dual damascene structure utilizing a developable anti-reflective coating Oct. 7, 2008
7413989 Method of manufacturing semiconductor device Aug. 19, 2008
7399697 Very low dielectric constant plasma-enhanced CVD films Jul. 15, 2008
7399671 Disposable pillars for contact formation Jul. 15, 2008
7381638 Fabrication technique using sputter etch and vacuum transfer Jun. 3, 2008
7375023 Method and apparatus for chemical mechanical polishing of semiconductor substrates May. 20, 2008
7371679 Semiconductor device with a metal line and method of forming the same May. 13, 2008
7371665 Method for fabricating shallow trench isolation layer of semiconductor device May. 13, 2008
7368383 Hillock reduction in copper films May. 6, 2008
7364997 Methods of forming integrated circuitry and methods of forming local interconnects Apr. 29, 2008
7348272 Method of fabricating interconnect Mar. 25, 2008
7338907 Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications Mar. 4, 2008
7327034 Compositions for planarization of metal-containing surfaces using halogens and halide salts Feb. 5, 2008
7323407 Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material Jan. 29, 2008
7316980 Method for forming ferrocapacitors and FeRAM devices Jan. 8, 2008
7314823 Chemical mechanical polishing composition and process Jan. 1, 2008
7303985 Zeolite-carbon doped oxide composite low k dielectric Dec. 4, 2007
7294569 Semiconductor device fabrication method and semiconductor device fabrication system for minimizing film-thickness variations Nov. 13, 2007
7294573 Method for controlling poly 1 thickness and uniformity in a memory array fabrication process Nov. 13, 2007
7291562 Method to form topography in a deposited layer above a substrate Nov. 6, 2007
7271088 Slurry composition with high planarity and CMP process of dielectric film using the same Sep. 18, 2007
7253097 Integrated circuit system using dual damascene process Aug. 7, 2007
7247558 Method and system for electroprocessing conductive layers Jul. 24, 2007
7247557 Method and composition to minimize dishing Jul. 24, 2007
7247256 CMP slurry for forming aluminum film, CMP method using the slurry, and method for forming aluminum wiring using the CMP method Jul. 24, 2007
7246424 Magnetic devices having magnetic features with CMP stop layers Jul. 24, 2007
7241692 Method and structure for aluminum chemical mechanical polishing and protective layer Jul. 10, 2007
7238606 Semiconductor devices and method for fabricating the same Jul. 3, 2007
7232752 Method of removing contaminants from a silicon wafer after chemical-mechanical polishing operation Jun. 19, 2007
7232746 Method for forming dual damascene interconnection in semiconductor device Jun. 19, 2007

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