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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.

Patents under this class:
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Patent Number Title Of Patent Date Issued
5595937 Method for fabricating semiconductor device with interconnections buried in trenches Jan. 21, 1997
5593919 Process for forming a semiconductor device including conductive members Jan. 14, 1997
5578523 Method for forming inlaid interconnects in a semiconductor device Nov. 26, 1996
5575885 Copper-based metal polishing solution and method for manufacturing semiconductor device Nov. 19, 1996
5573633 Method of chemically mechanically polishing an electronic component Nov. 12, 1996
5560802 Selective CMP of in-situ deposited multilayer films to enhance nonplanar step height reduction Oct. 1, 1996
5516729 Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate May. 14, 1996
5514616 Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures May. 7, 1996
5512514 Self-aligned via and contact interconnect manufacturing method Apr. 30, 1996
5502007 Method of forming flat surface of insulator film of semiconductor device Mar. 26, 1996
5498574 Process of fabricating semiconductor device having flattening stage for inter-level insulating layer without deterioration of device characteristics Mar. 12, 1996
5496771 Method of making overpass mask/insulator for local interconnects Mar. 5, 1996
5494854 Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO.sub.2 films Feb. 27, 1996
5491113 Method of manufacturing semiconductor device having a planarized surface Feb. 13, 1996
5468682 Method of manufacturing semiconductor device using the abrasive Nov. 21, 1995
5466639 Double mask process for forming trenches and contacts during the formation of a semiconductor memory device Nov. 14, 1995
5466639 Double mask process for forming trenches and contacts during the formation of a semiconductor memory device Nov. 14, 1995
5457070 Method of forming a step compensated semiconductor device Oct. 10, 1995
5451551 Multilevel metallization process using polishing Sep. 19, 1995
5449314 Method of chimical mechanical polishing for dielectric layers Sep. 12, 1995
5445996 Method for planarizing a semiconductor device having a amorphous layer Aug. 29, 1995
5401691 Method of fabrication an inverse open frame alignment mark Mar. 28, 1995
5401681 Method of forming a bit line over capacitor array of memory cells Mar. 28, 1995
5399235 Method of manufacturing a semiconductor device in which a surface of a semiconductor body is provided with mutually-insulated aluminum tracks Mar. 21, 1995
5399528 Multi-layer fabrication in integrated circuit systems Mar. 21, 1995
5397741 Process for metallized vias in polyimide Mar. 14, 1995
5395801 Chemical-mechanical polishing processes of planarizing insulating layers Mar. 7, 1995
5356513 Polishstop planarization method and structure Oct. 18, 1994
5332467 Chemical/mechanical polishing for ULSI planarization Jul. 26, 1994
5328553 Method for fabricating a semiconductor device having a planar surface Jul. 12, 1994
5312512 Global planarization using SOG and CMP May. 17, 1994
5302551 Method for planarizing the surface of an integrated circuit over a metal interconnect layer Apr. 12, 1994
5292689 Method for planarizing semiconductor structure using subminimum features Mar. 8, 1994
5283208 Method of making a submicrometer local structure using an organic mandrel Feb. 1, 1994
5270241 Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing Dec. 14, 1993
5268330 Process for improving sheet resistance of an integrated circuit device gate Dec. 7, 1993
5266446 Method of making a multilayer thin film structure Nov. 30, 1993
5244837 Semiconductor electrical interconnection methods Sep. 14, 1993
5244534 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs Sep. 14, 1993
5234868 Method for determining planarization endpoint during chemical-mechanical polishing Aug. 10, 1993
5229326 Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device Jul. 20, 1993
5229325 Method for forming metal wirings of semiconductor device Jul. 20, 1993
5173442 Methods of forming channels and vias in insulating layers Dec. 22, 1992
5143867 Method for depositing interconnection metallurgy using low temperature alloy processes Sep. 1, 1992
5104828 Method of planarizing a dielectric formed over a semiconductor substrate Apr. 14, 1992
4956313 Via-filling and planarization technique Sep. 11, 1990
4944836 Chem-mech polishing method for producing coplanar metal/insulator films on a substrate Jul. 31, 1990
4789648 Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias Dec. 6, 1988

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