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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.

Patents under this class:
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Patent Number Title Of Patent Date Issued
5783490 Photolithography alignment mark and manufacturing method Jul. 21, 1998
5783485 Process for fabricating a metallized interconnect Jul. 21, 1998
5780323 Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug Jul. 14, 1998
5776828 Reduced RC delay between adjacent substrate wiring lines Jul. 7, 1998
5773365 Fabrication process of semiconductor device Jun. 30, 1998
5770095 Polishing agent and polishing method using the same Jun. 23, 1998
5767016 Method of forming a wiring layer on a semiconductor by polishing with treated slurry Jun. 16, 1998
5767013 Method for forming interconnection in semiconductor pattern device Jun. 16, 1998
5767014 Integrated circuit and process for its manufacture Jun. 16, 1998
5759911 Self-aligned metallurgy Jun. 2, 1998
5759882 Method of fabricating self-aligned contacts and local interconnects in CMOS and BICMOS processes using chemical mechanical polishing (CMP) Jun. 2, 1998
5759906 Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits Jun. 2, 1998
5747382 Two-step planarization process using chemical-mechanical polishing and reactive-ion-etching May. 5, 1998
5744400 Apparatus and method for dry milling of non-planar features on a semiconductor surface Apr. 28, 1998
5741626 Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) Apr. 21, 1998
5726099 Method of chemically mechanically polishing an electronic component using a non-selective ammonium persulfate slurry Mar. 10, 1998
5723381 Formation of self-aligned overlapping bitline contacts with sacrificial polysilicon fill-in stud Mar. 3, 1998
5721172 Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers Feb. 24, 1998
5721157 Method for manufacturing a semiconductor device having interconnection layers Feb. 24, 1998
5718800 Self-aligned N+/P+ doped polysilicon plugged contacts to N+/P+ doped polysilicon gates and to N+/P+ doped source/drain regions Feb. 17, 1998
5716890 Structure and method for fabricating an interlayer insulating film Feb. 10, 1998
5705028 Method of manufacturing a semiconductor device with flattened multi-layer wirings Jan. 6, 1998
5702990 Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells Dec. 30, 1997
5702980 Method for forming intermetal dielectric with SOG etchback and CMP Dec. 30, 1997
5700706 Self-aligned isolated polysilicon plugged contacts Dec. 23, 1997
5700348 Method of polishing semiconductor substrate Dec. 23, 1997
5698467 Method of manufacturing an insulation layer having a flat surface Dec. 16, 1997
5688720 Method of flattening the surface of a semiconductor device by polishing Nov. 18, 1997
5686356 Conductor reticulation for improved device planarity Nov. 11, 1997
5681423 Semiconductor wafer for improved chemical-mechanical polishing over large area features Oct. 28, 1997
5681425 Teos plasma protection technology Oct. 28, 1997
5677239 Method for fabricating multi-level interconnection structure for semiconductor device Oct. 14, 1997
5674783 Method for improving the chemical-mechanical polish (CMP) uniformity of insulator layers Oct. 7, 1997
5674352 Process related to a modified polishing pad for polishing Oct. 7, 1997
5670409 Method of fabricating a semiconductor IC DRAM device enjoying enhanced focus margin Sep. 23, 1997
5662769 Chemical solutions for removing metal-compound contaminants from wafers after CMP and the method of wafer cleaning Sep. 2, 1997
5663108 Optimized metal pillar via process Sep. 2, 1997
5663102 Method for forming multi-layered metal wiring semiconductor element using cmp or etch back Sep. 2, 1997
5658830 Method for fabricating interconnecting lines and contacts using conformal deposition Aug. 19, 1997
5654216 Formation of a metal via structure from a composite metal layer Aug. 5, 1997
5648298 Methods for forming a contact in a semiconductor device Jul. 15, 1997
5639697 Dummy underlayers for improvement in removal rate consistency during chemical mechanical polishing Jun. 17, 1997
5633207 Method of forming a wiring layer for a semiconductor device May. 27, 1997
5629224 Resist/etchback planarizing techniques for fabricating semiconductor devices based on CMOS structures May. 13, 1997
5626715 Methods of polishing semiconductor substrates May. 6, 1997
5618381 Multiple step method of chemical-mechanical polishing which minimizes dishing Apr. 8, 1997
5616519 Non-etch back SOG process for hot aluminum metallizations Apr. 1, 1997
5607873 Method for forming contact openings in a multi-layer structure that reduces overetching of the top conductive structure Mar. 4, 1997
5604156 Wire forming method for semiconductor device Feb. 18, 1997
5597764 Method of contact formation and planarization for semiconductor processes Jan. 28, 1997

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