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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 5891805 |
Method of forming contacts |
Apr. 6, 1999 |
| 5888896 |
Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component |
Mar. 30, 1999 |
| 5888900 |
Method for manufacturing semiconductor device and reticle for wiring |
Mar. 30, 1999 |
| 5885894 |
Method of planarizing an inter-layer dielectric layer |
Mar. 23, 1999 |
| 5882999 |
Process for metallization of an insulation layer |
Mar. 16, 1999 |
| 5880018 |
Method for manufacturing a low dielectric constant inter-level integrated circuit structure |
Mar. 9, 1999 |
| 5880039 |
Method for forming interlayer insulating film of a semiconductor device |
Mar. 9, 1999 |
| 5880024 |
Semiconductor device having wiring self-aligned with shield structure and process of fabrication thereof |
Mar. 9, 1999 |
| 5872053 |
Method of forming an enlarged head on a plug to eliminate the enclosure requirement |
Feb. 16, 1999 |
| 5869392 |
Method of fabricating a semiconductor device including a plurality of contact regions disposed at different depths |
Feb. 9, 1999 |
| 5866477 |
Method of polishing a chamfered portion of a semiconductor silicon substrate |
Feb. 2, 1999 |
| 5861342 |
Optimized structures for dummy fill mask design |
Jan. 19, 1999 |
| 5861676 |
Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit |
Jan. 19, 1999 |
| 5858870 |
Methods for gap fill and planarization of intermetal dielectrics |
Jan. 12, 1999 |
| 5858833 |
Methods for manufacturing integrated circuit memory devices including trench buried bit lines |
Jan. 12, 1999 |
| 5854130 |
Method of forming multilevel interconnects in semiconductor devices |
Dec. 29, 1998 |
| 5854140 |
Method of making an aluminum contact |
Dec. 29, 1998 |
| 5851916 |
Formation of a self-aligned integrated circuit structures using planarization to form a top surface |
Dec. 22, 1998 |
| 5849637 |
Integration of spin-on gap filling dielectric with W-plug without outgassing |
Dec. 15, 1998 |
| 5849632 |
Method of passivating semiconductor wafers |
Dec. 15, 1998 |
| 5846876 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines |
Dec. 8, 1998 |
| 5843834 |
Self-aligned POCL.sub.3 process flow for submicron microelectronics applications using amorphized polysilicon |
Dec. 1, 1998 |
| 5840625 |
Method of fabricating integrated circuit interconnection employing tungsten/aluminum layers |
Nov. 24, 1998 |
| 5840623 |
Efficient and economical method of planarization of multilevel metallization structures in integrated circuits using CMP |
Nov. 24, 1998 |
| 5836806 |
Slurries for chemical mechanical polishing |
Nov. 17, 1998 |
| 5821164 |
Method for forming metal line |
Oct. 13, 1998 |
| 5821168 |
Process for forming a semiconductor device |
Oct. 13, 1998 |
| 5817572 |
Method for forming multileves interconnections for semiconductor fabrication |
Oct. 6, 1998 |
| 5814557 |
Method of forming an interconnect structure |
Sep. 29, 1998 |
| 5804503 |
Method and structure for reducing microelectronic short circuits using spin-on glass as part of the interlayer dielectric |
Sep. 8, 1998 |
| 5804084 |
Use of chemical mechanical polishing in micromachining |
Sep. 8, 1998 |
| 5801094 |
Dual damascene process |
Sep. 1, 1998 |
| 5801095 |
Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology |
Sep. 1, 1998 |
| 5801090 |
Method of protecting an alignment mark in a semiconductor manufacturing process with CMP |
Sep. 1, 1998 |
| 5792707 |
Global planarization method for inter level dielectric layers of integrated circuits |
Aug. 11, 1998 |
| 5789290 |
Polysilicon CMP process for high-density DRAM cell structures |
Aug. 4, 1998 |
| 5783485 |
Process for fabricating a metallized interconnect |
Jul. 21, 1998 |
| 5783490 |
Photolithography alignment mark and manufacturing method |
Jul. 21, 1998 |
| 5780323 |
Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug |
Jul. 14, 1998 |
| 5776828 |
Reduced RC delay between adjacent substrate wiring lines |
Jul. 7, 1998 |
| 5773365 |
Fabrication process of semiconductor device |
Jun. 30, 1998 |
| 5770095 |
Polishing agent and polishing method using the same |
Jun. 23, 1998 |
| 5767013 |
Method for forming interconnection in semiconductor pattern device |
Jun. 16, 1998 |
| 5767014 |
Integrated circuit and process for its manufacture |
Jun. 16, 1998 |
| 5767016 |
Method of forming a wiring layer on a semiconductor by polishing with treated slurry |
Jun. 16, 1998 |
| 5759911 |
Self-aligned metallurgy |
Jun. 2, 1998 |
| 5759906 |
Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits |
Jun. 2, 1998 |
| 5759882 |
Method of fabricating self-aligned contacts and local interconnects in CMOS and BICMOS processes using chemical mechanical polishing (CMP) |
Jun. 2, 1998 |
| 5747382 |
Two-step planarization process using chemical-mechanical polishing and reactive-ion-etching |
May. 5, 1998 |
| 5744400 |
Apparatus and method for dry milling of non-planar features on a semiconductor surface |
Apr. 28, 1998 |
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