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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.










Patents under this class:
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Patent Number Title Of Patent Date Issued
5924006 Trench surrounded metal pattern Jul. 13, 1999
5920792 High density plasma enhanced chemical vapor deposition process in combination with chemical mechanical polishing process for preparation and planarization of intemetal dielectric layers Jul. 6, 1999
5915203 Method for producing deep submicron interconnect vias Jun. 22, 1999
5913141 Reliable interconnect via structures and methods for making the same Jun. 15, 1999
5910020 Method for fabricating a semiconductor device having a refractory metal pillar for electrical connection Jun. 8, 1999
5907787 Process for fabricating multilayer connection May. 25, 1999
5904559 Three dimensional contact or via structure with multiple sidewall contacts May. 18, 1999
5904557 Method for forming multilevel interconnection of semiconductor device May. 18, 1999
5904558 Fabrication process of semiconductor device May. 18, 1999
5897371 Alignment process compatible with chemical mechanical polishing Apr. 27, 1999
5895263 Process for manufacture of integrated circuit device Apr. 20, 1999
5893750 Method for forming a highly planarized interlevel dielectric structure Apr. 13, 1999
5891513 Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications Apr. 6, 1999
5891805 Method of forming contacts Apr. 6, 1999
5891799 Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates Apr. 6, 1999
5888900 Method for manufacturing semiconductor device and reticle for wiring Mar. 30, 1999
5888896 Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component Mar. 30, 1999
5885894 Method of planarizing an inter-layer dielectric layer Mar. 23, 1999
5882999 Process for metallization of an insulation layer Mar. 16, 1999
5880024 Semiconductor device having wiring self-aligned with shield structure and process of fabrication thereof Mar. 9, 1999
5880018 Method for manufacturing a low dielectric constant inter-level integrated circuit structure Mar. 9, 1999
5880039 Method for forming interlayer insulating film of a semiconductor device Mar. 9, 1999
5872053 Method of forming an enlarged head on a plug to eliminate the enclosure requirement Feb. 16, 1999
5869392 Method of fabricating a semiconductor device including a plurality of contact regions disposed at different depths Feb. 9, 1999
5866477 Method of polishing a chamfered portion of a semiconductor silicon substrate Feb. 2, 1999
5861676 Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit Jan. 19, 1999
5861342 Optimized structures for dummy fill mask design Jan. 19, 1999
5858833 Methods for manufacturing integrated circuit memory devices including trench buried bit lines Jan. 12, 1999
5858870 Methods for gap fill and planarization of intermetal dielectrics Jan. 12, 1999
5854140 Method of making an aluminum contact Dec. 29, 1998
5854130 Method of forming multilevel interconnects in semiconductor devices Dec. 29, 1998
5851916 Formation of a self-aligned integrated circuit structures using planarization to form a top surface Dec. 22, 1998
5849632 Method of passivating semiconductor wafers Dec. 15, 1998
5849637 Integration of spin-on gap filling dielectric with W-plug without outgassing Dec. 15, 1998
5846876 Integrated circuit which uses a damascene process for producing staggered interconnect lines Dec. 8, 1998
5843834 Self-aligned POCL.sub.3 process flow for submicron microelectronics applications using amorphized polysilicon Dec. 1, 1998
5840625 Method of fabricating integrated circuit interconnection employing tungsten/aluminum layers Nov. 24, 1998
5840623 Efficient and economical method of planarization of multilevel metallization structures in integrated circuits using CMP Nov. 24, 1998
5836806 Slurries for chemical mechanical polishing Nov. 17, 1998
5821164 Method for forming metal line Oct. 13, 1998
5821168 Process for forming a semiconductor device Oct. 13, 1998
5817572 Method for forming multileves interconnections for semiconductor fabrication Oct. 6, 1998
5814557 Method of forming an interconnect structure Sep. 29, 1998
5804503 Method and structure for reducing microelectronic short circuits using spin-on glass as part of the interlayer dielectric Sep. 8, 1998
5804084 Use of chemical mechanical polishing in micromachining Sep. 8, 1998
5801094 Dual damascene process Sep. 1, 1998
5801090 Method of protecting an alignment mark in a semiconductor manufacturing process with CMP Sep. 1, 1998
5801095 Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology Sep. 1, 1998
5792707 Global planarization method for inter level dielectric layers of integrated circuits Aug. 11, 1998
5789290 Polysilicon CMP process for high-density DRAM cell structures Aug. 4, 1998

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