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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.

Patents under this class:
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Patent Number Title Of Patent Date Issued
6127261 Method of fabricating an integrated circuit including a tri-layer pre-metal interlayer dielectric compatible with advanced CMOS technologies Oct. 3, 2000
6124189 Metallization structure and method for a semiconductor device Sep. 26, 2000
6117798 Method of spin-on-glass planarization Sep. 12, 2000
6117770 Method for implanting semiconductor conductive layers Sep. 12, 2000
6117766 Method of forming contact plugs in a semiconductor device Sep. 12, 2000
6117760 Method of making a high density interconnect formation Sep. 12, 2000
6114234 Method of making a semiconductor with copper passivating film Sep. 5, 2000
6114235 Multipurpose cap layer dielectric Sep. 5, 2000
6114243 Method to avoid copper contamination on the sidewall of a via or a dual damascene structure Sep. 5, 2000
6114242 MOCVD molybdenum nitride diffusion barrier for Cu metallization Sep. 5, 2000
6114215 Generating non-planar topology on the surface of planar and near-planar substrates Sep. 5, 2000
6110820 Low scratch density chemical mechanical planarization process Aug. 29, 2000
6107188 Passivation method for copper process Aug. 22, 2000
6107187 Method for forming a semiconductor device Aug. 22, 2000
6107186 High planarity high-density in-laid metallization patterns by damascene-CMP processing Aug. 22, 2000
6107185 Conductive material adhesion enhancement in damascene process for semiconductors Aug. 22, 2000
6103617 Fabricating method of multi-level wiring structure for semiconductor device Aug. 15, 2000
6103618 Method for forming an interconnection in a semiconductor element Aug. 15, 2000
6100196 Method of making a copper interconnect with top barrier layer Aug. 8, 2000
6100181 Low dielectric constant coating of conductive material in a damascene process for semiconductors Aug. 8, 2000
6100180 Formation of a self-aligned integrated circuit structure using planarization to form a top surface Aug. 8, 2000
6096635 Method for creating via hole in chip Aug. 1, 2000
6096632 Fabrication method of semiconductor device using CMP process Aug. 1, 2000
6096654 Gapfill of semiconductor structure using doped silicate glasses Aug. 1, 2000
6093656 Method of minimizing dishing during chemical mechanical polishing of semiconductor metals for making a semiconductor device Jul. 25, 2000
6093650 Method for fully planarized conductive line for a stack gate Jul. 25, 2000
6093639 Process for making contact plug Jul. 25, 2000
6093631 Dummy patterns for aluminum chemical polishing (CMP) Jul. 25, 2000
6090701 Method for production of semiconductor device Jul. 18, 2000
6083824 Borderless contact Jul. 4, 2000
6080659 Method to form an alignment mark Jun. 27, 2000
6080655 Method for fabricating conductive components in microelectronic devices and substrate structures thereof Jun. 27, 2000
6077770 Damascene manufacturing process capable of forming borderless via Jun. 20, 2000
6074907 Method of manufacturing capacitor for analog function Jun. 13, 2000
6071808 Method of passivating copper interconnects in a semiconductor Jun. 6, 2000
6071809 Methods for forming high-performing dual-damascene interconnect structures Jun. 6, 2000
6069047 Method of making damascene completely self aligned ultra short channel MOS transistor May. 30, 2000
6054397 BPSG planarization method having improved planarity and reduced chatter mark defects Apr. 25, 2000
6054383 Fabrication method of semiconductor device Apr. 25, 2000
6051495 Seasoning of a semiconductor wafer polishing pad to polish tungsten Apr. 18, 2000
6051467 Method to fabricate a large planar area ONO interpoly dielectric in flash device Apr. 18, 2000
6051496 Use of stop layer for chemical mechanical polishing of CU damascene Apr. 18, 2000
6051477 Method of fabricating semiconductor device Apr. 18, 2000
6048789 IC interconnect formation with chemical-mechanical polishing and silica etching with solution of nitric and hydrofluoric acids Apr. 11, 2000
6048800 Process for planarizing surface of a semiconductor device Apr. 11, 2000
6046108 Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby Apr. 4, 2000
6040240 Method for forming interconnection structure Mar. 21, 2000
6037250 Process for forming multilevel interconnection structure Mar. 14, 2000
6037253 Method for increasing interconnect packing density in integrated circuits Mar. 14, 2000
6033981 Keyhole-free process for high aspect ratio gap filing Mar. 7, 2000

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