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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6204169 Processing for polishing dissimilar conductive layers in a semiconductor device Mar. 20, 2001
6204096 Method for reducing critical dimension of dual damascene process using spin-on-glass process Mar. 20, 2001
6204165 Practical air dielectric interconnections by post-processing standard CMOS wafers Mar. 20, 2001
6200901 Polishing polymer surfaces on non-porous CMP pads Mar. 13, 2001
6197682 Structure of a contact hole in a semiconductor device and method of manufacturing the same Mar. 6, 2001
6197690 Chemically preventing Cu dendrite formation and growth by double sided scrubbing Mar. 6, 2001
6197678 Damascene process Mar. 6, 2001
6194317 Method of planarizing the upper surface of a semiconductor wafer Feb. 27, 2001
6194287 Shallow trench isolation (STI) method with reproducible alignment registration Feb. 27, 2001
6191029 Damascene process Feb. 20, 2001
6191028 Method of patterning dielectric Feb. 20, 2001
6191027 Method of forming flat wiring layer Feb. 20, 2001
6191025 Method of fabricating a damascene structure for copper medullization Feb. 20, 2001
6187666 CVD plasma process to fill contact hole in damascene process Feb. 13, 2001
6184128 Method using a thin resist mask for dual damascene stop layer etch Feb. 6, 2001
6184138 Method to create a controllable and reproducible dual copper damascene structure Feb. 6, 2001
6184143 Semiconductor integrated circuit device and fabrication process thereof Feb. 6, 2001
6184124 Method of making embedded wiring system Feb. 6, 2001
6180509 Method for forming planarized multilevel metallization in an integrated circuit Jan. 30, 2001
6180514 Method for forming interconnect using dual damascene Jan. 30, 2001
6180506 Upper redundant layer for damascene metallization Jan. 30, 2001
6177338 Two step barrier process Jan. 23, 2001
6177360 Process for manufacture of integrated circuit device Jan. 23, 2001
6177342 Method of forming dual damascene interconnects using glue material as plug material Jan. 23, 2001
6174804 Dual damascene manufacturing process Jan. 16, 2001
6174777 Method for fabricating a self aligned contact using a reverse self aligned contact etch Jan. 16, 2001
6171949 Low energy passivation of conductive material in damascene process for semiconductors Jan. 9, 2001
6165893 Insulating layers and a forming method thereof Dec. 26, 2000
6165895 Fabrication method of an interconnect Dec. 26, 2000
6162728 Method to optimize copper chemical-mechanical polishing in a copper damascene interconnect process for integrated circuit applications Dec. 19, 2000
6159843 Method of fabricating landing pad Dec. 12, 2000
6160314 Polishing stop structure Dec. 12, 2000
6156651 Metallization method for porous dielectrics Dec. 5, 2000
6156631 Method of manufacturing semiconductor device Dec. 5, 2000
6153514 Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer Nov. 28, 2000
6153507 Method of fabricating semiconductor device providing effective resistance against metal layer oxidation and diffusion Nov. 28, 2000
6153525 Methods for chemical mechanical polish of organic polymer dielectric films Nov. 28, 2000
6146987 Method for forming a contact plug over an underlying metal line using an etching stop layer Nov. 14, 2000
6146992 Vertically integrated semiconductor component and method of producing the same Nov. 14, 2000
6146994 Method for forming self-aligned selective silicide layer using chemical mechanical polishing in merged DRAM logic Nov. 14, 2000
6146988 Method of making a semiconductor device comprising copper interconnects with reduced in-line copper diffusion Nov. 14, 2000
6143656 Slurry for chemical mechanical polishing of copper Nov. 7, 2000
6143648 Method for forming an integrated circuit Nov. 7, 2000
6140224 Method of forming a tungsten plug Oct. 31, 2000
6136693 Method for planarized interconnect vias using electroless plating and CMP Oct. 24, 2000
6133139 Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof Oct. 17, 2000
6133133 Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component Oct. 17, 2000
6129819 Method for depositing high density plasma chemical vapor deposition oxide in high aspect ratio gaps Oct. 10, 2000
6130157 Method to form an encapsulation layer over copper interconnects Oct. 10, 2000
6127264 Integrated circuit having conductors of enhanced cross-sectional area Oct. 3, 2000

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