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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6274478 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process Aug. 14, 2001
6274479 Flowable germanium doped silicate glass for use as a spacer oxide Aug. 14, 2001
6274509 Global planarization method for inter-layer-dielectric and inter-metal dielectric Aug. 14, 2001
6274483 Method to improve metal line adhesion by trench corner shape modification Aug. 14, 2001
6274480 Method of Fabricating semiconductor device Aug. 14, 2001
6271118 Method of applying partial reverse mask Aug. 7, 2001
6271106 Method of manufacturing a semiconductor component Aug. 7, 2001
6271123 Chemical-mechanical polish method using an undoped silicon glass stop layer for polishing BPSG Aug. 7, 2001
6271124 Method of making a dynamic random access memory device utilizing chemical mechanical polishing Aug. 7, 2001
6271120 Method of enhanced silicide layer for advanced metal diffusion barrier layer application Aug. 7, 2001
6271132 Self-aligned source and drain extensions fabricated in a damascene contact and gate process Aug. 7, 2001
6268277 Method of producing air gap for reducing intralayer capacitance in metal layers in damascene metalization process and product resulting therefrom Jul. 31, 2001
6263586 Device and method for planarizing a thin film Jul. 24, 2001
6265307 Fabrication method for a dual damascene structure Jul. 24, 2001
6261905 Flash memory structure with stacking gate formed using damascene-like structure Jul. 17, 2001
6261945 Crackstop and oxygen barrier for low-K dielectric integrated circuits Jul. 17, 2001
6261950 Self-aligned metal caps for interlevel metal connections Jul. 17, 2001
6261954 Method to deposit a copper layer Jul. 17, 2001
6258711 Sacrificial deposit to improve damascene pattern planarization in semiconductor wafers Jul. 10, 2001
6255211 Silicon carbide stop layer in chemical mechanical polishing over metallization layers Jul. 3, 2001
6251789 Selective slurries for the formation of conductive structures Jun. 26, 2001
6251781 Method to deposit a platinum seed layer for use in selective copper plating Jun. 26, 2001
6251773 Method of designing and structure for visual and electrical test of semiconductor devices Jun. 26, 2001
6248660 Method for forming metallic plug Jun. 19, 2001
6245653 Method of filling an opening in an insulating layer Jun. 12, 2001
6245669 High selectivity Si-rich SiON etch-stop layer Jun. 12, 2001
6242343 Process for fabricating semiconductor device and apparatus for fabricating semiconductor device Jun. 5, 2001
6242337 Semiconductor device and method of manufacturing the same Jun. 5, 2001
6239020 Method for forming interlayer dielectric layer May. 29, 2001
6235632 Tungsten plug formation May. 22, 2001
6235633 Method for making tungsten metal plugs in a polymer low-K intermetal dielectric layer using an improved two-step chemical/mechanical polishing process May. 22, 2001
6228759 Method of forming an alloy precipitate to surround interconnect to minimize electromigration May. 8, 2001
6228711 Method of fabricating dynamic random access memory May. 8, 2001
6228707 Semiconductor arrangement having capacitive structure and manufacture thereof May. 8, 2001
6221704 Process for fabricating short channel field effect transistor with a highly conductive gate Apr. 24, 2001
6221759 Method for forming aligned vias under trenches in a dual damascene process Apr. 24, 2001
6221777 Reverse lithographic process for semiconductor vias Apr. 24, 2001
6218290 Copper dendrite prevention by chemical removal of dielectric Apr. 17, 2001
6218286 Isolation dielectric deposition in multi-polysilicon chemical-mechanical polishing process Apr. 17, 2001
6218284 Method for forming an inter-metal dielectric layer Apr. 17, 2001
6218291 Method for forming contact plugs and simultaneously planarizing a substrate surface in integrated circuits Apr. 17, 2001
6211067 Method for manufacturing metal plug Apr. 3, 2001
6211084 Method of forming reliable copper interconnects Apr. 3, 2001
6211057 Method for manufacturing arch air gap in multilevel interconnection Apr. 3, 2001
6207555 Electron beam process during dual damascene processing Mar. 27, 2001
6207569 Prevention of Cu dendrite formation and growth Mar. 27, 2001
6207571 Self-aligned contact formation for semiconductor devices Mar. 27, 2001
6207630 Processing compositions and methods of using same Mar. 27, 2001
6207554 Gap filling process in integrated circuits using low dielectric constant materials Mar. 27, 2001
6204195 Method to prevent CMP overpolish Mar. 20, 2001

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