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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.

Patents under this class:
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Patent Number Title Of Patent Date Issued
6352913 Damascene process for MOSFET fabrication Mar. 5, 2002
6352899 Raised silicide source/drain MOS transistors having enlarged source/drain contact regions and method Mar. 5, 2002
6350658 Method for realizing alignment marks on a semiconductor device during a manufacturing process including at least a chemical mechanical polishing process step Feb. 26, 2002
6350678 Chemical-mechanical polishing of semiconductors Feb. 26, 2002
6350691 Method and apparatus for planarizing microelectronic substrates and conditioning planarizing media Feb. 26, 2002
6350688 Via RC improvement for copper damascene and beyond technology Feb. 26, 2002
6350682 Method of fabricating dual damascene structure using a hard mask Feb. 26, 2002
6348406 Method for using a low dielectric constant layer as a semiconductor anti-reflective coating Feb. 19, 2002
6348410 Low temperature hillock suppression method in integrated circuit interconnects Feb. 19, 2002
6348415 Planarization method for semiconductor device Feb. 19, 2002
6348414 Method for forming fine metal patterns by using damascene technique Feb. 19, 2002
6346474 Dual damascene process Feb. 12, 2002
6344408 Method for improving non-uniformity of chemical mechanical polishing by over coating Feb. 5, 2002
6344409 Dummy patterns for aluminum chemical polishing (CMP) Feb. 5, 2002
6342454 Electronic devices with dielectric compositions and method for their manufacture Jan. 29, 2002
6340601 Method for reworking copper metallurgy in semiconductor devices Jan. 22, 2002
6340638 Method for forming a passivation layer on copper conductive elements Jan. 22, 2002
6340636 Method for forming metal line in semiconductor device Jan. 22, 2002
6331481 Damascene etchback for low .epsilon. dielectric Dec. 18, 2001
6329284 Manufacturing process of a semiconductor device Dec. 11, 2001
6326305 Ceria removal in chemical-mechanical polishing of integrated circuits Dec. 4, 2001
6326299 Method for manufacturing a semiconductor device Dec. 4, 2001
6323121 Fully dry post-via-etch cleaning method for a damascene process Nov. 27, 2001
6319819 Process for passivating top interface of damascene-type Cu interconnect lines Nov. 20, 2001
6319820 Fabrication method for dual damascene structure Nov. 20, 2001
6319823 Process for forming a borderless via in a semiconductor device Nov. 20, 2001
6319833 Chemically preventing copper dendrite formation and growth by spraying Nov. 20, 2001
6316356 Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication Nov. 13, 2001
6313024 Method for forming a semiconductor device Nov. 6, 2001
6309956 Fabricating low K dielectric interconnect systems by using dummy structures to enhance process Oct. 30, 2001
6309961 Method of forming damascene wiring in a semiconductor device Oct. 30, 2001
6309959 Formation of self-aligned passivation for interconnect to minimize electromigration Oct. 30, 2001
6309964 Method for forming a copper damascene structure over tungsten plugs with improved adhesion, oxidation resistance, and diffusion barrier properties using nitridation of the tungsten plug Oct. 30, 2001
6306755 Method for endpoint detection during dry etch of submicron features in a semiconductor device Oct. 23, 2001
6306754 Method for forming wiring with extremely low parasitic capacitance Oct. 23, 2001
6303431 Method of fabricating bit lines Oct. 16, 2001
6303551 Cleaning solution and method for cleaning semiconductor substrates after polishing of cooper film Oct. 16, 2001
6303505 Copper interconnect with improved electromigration resistance Oct. 16, 2001
6303484 Method of manufacturing dummy pattern Oct. 16, 2001
6300241 Silicon interconnect passivation and metallization process optimized to maximize reflectance Oct. 9, 2001
6300239 Method of manufacturing semiconductor device Oct. 9, 2001
6297158 Stress management of barrier metal for resolving CU line corrosion Oct. 2, 2001
6294460 Semiconductor manufacturing method using a high extinction coefficient dielectric photomask Sep. 25, 2001
6291335 Locally folded split level bitline wiring Sep. 18, 2001
6291339 Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same Sep. 18, 2001
6291331 Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue Sep. 18, 2001
6284645 Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process Sep. 4, 2001
6284647 Method to improve the uniformity of chemical mechanical polishing Sep. 4, 2001
6281121 Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal Aug. 28, 2001
6281114 Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication Aug. 28, 2001

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