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Class Information
Number: 438/633
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Simultaneously by chemical and mechanical means
Description: Processes wherein the planarization step is conducted by the simultaneous chemical and mechanical material removal.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6417093 Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing Jul. 9, 2002
6417094 Dual-damascene interconnect structures and methods of fabricating same Jul. 9, 2002
6410418 Recess metallization via selective insulator formation on nucleation/seed layer Jun. 25, 2002
6410435 Process for fabricating copper interconnect for ULSI integrated circuits Jun. 25, 2002
6403469 Method of manufacturing dual damascene structure Jun. 11, 2002
6403470 Method for fabricating a dual damascene structure Jun. 11, 2002
6403468 Method for forming embedded metal wiring Jun. 11, 2002
6403466 Post-CMP-Cu deposition and CMP to eliminate surface voids Jun. 11, 2002
6403465 Method to improve copper barrier properties Jun. 11, 2002
6403424 Method for forming self-aligned mask read only memory by dual damascene trenches Jun. 11, 2002
6400030 Self-aligning vias for semiconductors Jun. 4, 2002
6399496 Copper interconnection structure incorporating a metal seed layer Jun. 4, 2002
6395620 Method for forming a planar surface over low density field areas on a semiconductor wafer May. 28, 2002
6395631 Low dielectric constant dielectric layer fabrication method employing hard mask layer delamination May. 28, 2002
6391768 Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure May. 21, 2002
6391745 Method for forming overlay verniers for semiconductor devices May. 21, 2002
6387770 Thin-film capacitors and methods for forming the same May. 14, 2002
6387791 Method for manufacturing microscopic canals within a semiconductor May. 14, 2002
6387797 Method for reducing the capacitance between interconnects by forming voids in dielectric material May. 14, 2002
6383914 Method of manufacturing an aluminum interconnect structure of a semiconductor device having <111> orientation May. 7, 2002
6383935 Method of reducing dishing and erosion using a sacrificial layer May. 7, 2002
6383930 Method to eliminate copper CMP residue of an alignment mark for damascene processes May. 7, 2002
6384482 Method for forming a dielectric layer in a semiconductor device by using etch stop layers May. 7, 2002
6383928 Post copper CMP clean May. 7, 2002
6380625 Semiconductor interconnect barrier and manufacturing method thereof Apr. 30, 2002
6380071 Method of fabricating semiconductor device Apr. 30, 2002
6380069 Method of removing micro-scratch on metal layer Apr. 30, 2002
6380074 Deposition of various base layers for selective layer growth in semiconductor production Apr. 30, 2002
6376361 Method to remove excess metal in the formation of damascene and dual interconnects Apr. 23, 2002
6376344 Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device Apr. 23, 2002
6376367 Method for manufacturing multilayer interconnects by forming a trench with an underlying through-hole in a low dielectric constant insulator layer Apr. 23, 2002
6376362 Production of semiconductor device Apr. 23, 2002
6376363 Forming method of copper interconnection and semiconductor wafer with copper interconnection formed thereon Apr. 23, 2002
6372648 Integrated circuit planarization method Apr. 16, 2002
6372638 Method for forming a conductive plug between conductive layers of an integrated circuit Apr. 16, 2002
6372630 Semiconductor device and fabrication method thereof Apr. 16, 2002
6368955 Method of polishing semiconductor structures using a two-step chemical mechanical planarization with slurry particles having different particle bulk densities Apr. 9, 2002
6368956 Method of manufacturing a semiconductor device Apr. 9, 2002
6368981 Method of manufacturing semiconductor device and chemical mechanical polishing apparatus Apr. 9, 2002
6365015 Method for depositing high density plasma chemical vapor deposition oxide in high aspect ratio gaps Apr. 2, 2002
6362092 Planarization method on a damascene structure Mar. 26, 2002
6362093 Dual damascene method employing sacrificial via fill layer Mar. 26, 2002
6358845 Method for forming inter metal dielectric Mar. 19, 2002
6358842 Method to form damascene interconnects with sidewall passivation to protect organic dielectrics Mar. 19, 2002
6358839 Solution to black diamond film delamination problem Mar. 19, 2002
6358832 Method of forming barrier layers for damascene interconnects Mar. 19, 2002
6358841 Method of copper CMP on low dielectric constant HSQ material Mar. 19, 2002
6355563 Versatile copper-wiring layout design with low-k dielectric integration Mar. 12, 2002
6355555 Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer Mar. 12, 2002
6352917 Reversed damascene process for multiple level metal interconnects Mar. 5, 2002

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