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Class Information
Number: 438/632
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Having planarization step > Utilizing reflow
Description: Processes wherein the planarization step is conducted by decreasing the viscosity of a layer and causing a leveling of the same by the viscous flow thereof.

Patents under this class:
1 2 3 4

Patent Number Title Of Patent Date Issued
8513112 Barrier-metal-free copper damascene technology using enhanced reflow Aug. 20, 2013
8436252 Printed wiring board and method for manufacturing the same May. 7, 2013
8211792 Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow Jul. 3, 2012
7994034 Temperature and pressure control methods to fill features with programmable resistance and switching devices Aug. 9, 2011
7888261 Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow Feb. 15, 2011
7829393 Copper gate electrode of liquid crystal display device and method of fabricating the same Nov. 9, 2010
7825026 Method for processing copper surface, method for forming copper pattern wiring and semiconductor device manufactured using such method Nov. 2, 2010
7648904 Metal line in semiconductor device and method for forming the same Jan. 19, 2010
RE40965 Method of forming low-resistance contact electrodes in semiconductor devices Nov. 10, 2009
7553748 Semiconductor device and method of manufacturing the same Jun. 30, 2009
7524697 Method for manufactuing a semiconductor integrated circuit device Apr. 28, 2009
7510961 Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure Mar. 31, 2009
7465977 Method for producing a packaged integrated circuit Dec. 16, 2008
7413979 Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices Aug. 19, 2008
7316974 Wiring pattern formation method, manufacturing method for multi layer wiring substrate, and electronic device Jan. 8, 2008
7288472 Method and system for performing die attach using a flame Oct. 30, 2007
7265044 Method for forming bump on electrode pad with use of double-layered film Sep. 4, 2007
7199043 Method of forming copper wiring in semiconductor device Apr. 3, 2007
7188411 Process for forming portions of a compound material inside a cavity Mar. 13, 2007
7186643 Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow Mar. 6, 2007
7172962 Method of manufacturing a semiconductor device Feb. 6, 2007
7164191 Low relative permittivity SiO.sub.x film including a porous material for use with a semiconductor device Jan. 16, 2007
7144808 Integration flow to prevent delamination from copper Dec. 5, 2006
7091124 Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices Aug. 15, 2006
6987060 Semiconductor device having improved contact hole structure and method for fabricating the same Jan. 17, 2006
6982223 Method of manufacturing a semiconductor device Jan. 3, 2006
6977213 IC chip solder bump structure and method of manufacturing same Dec. 20, 2005
6969301 Filling plugs through chemical mechanical polish Nov. 29, 2005
6949464 Contact/via force fill techniques Sep. 27, 2005
6936534 Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallization Aug. 30, 2005
6900121 Laser thermal annealing to eliminate oxide voiding May. 31, 2005
6893957 Method of forming a dual damascene interconnect by selective metal deposition May. 17, 2005
6878594 Semiconductor device having an insulation film with reduced water content Apr. 12, 2005
6872653 Manufacturing method of semiconductor device Mar. 29, 2005
6858530 Method for electrically characterizing charge sensitive semiconductor devices Feb. 22, 2005
6806208 Semiconductor device structured to prevent oxide damage during HDP CVD Oct. 19, 2004
6803308 Method of forming a dual damascene pattern in a semiconductor device Oct. 12, 2004
6787468 Method of fabricating metal lines in a semiconductor device Sep. 7, 2004
6746888 Display and fabricating method thereof Jun. 8, 2004
6727176 Method of forming reliable Cu interconnects Apr. 27, 2004
6716739 Bump manufacturing method Apr. 6, 2004
6703321 Low thermal budget solution for PMD application using sacvd layer Mar. 9, 2004
6696360 Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow Feb. 24, 2004
6667232 Thin dielectric layers and non-thermal formation thereof Dec. 23, 2003
6620534 Film having enhanced reflow characteristics at low thermal budget Sep. 16, 2003
6602788 Process for fabricating an interconnect for contact holes Aug. 5, 2003
6599828 Copper reflow process Jul. 29, 2003
6594894 Planar-processing compatible metallic micro-extrusion process Jul. 22, 2003
6546306 Method for adjusting incoming film thickness uniformity such that variations across the film after polishing minimized Apr. 8, 2003
6534396 Patterned conductor layer pasivation method with dimensionally stabilized planarization Mar. 18, 2003

1 2 3 4

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