| |
 |
|
Class Information
Number: 438/629
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > At least one metallization level formed of diverse conductive layers > Diverse conductive layers limited to viahole/plug
Description: Processes wherein the diverse conductive layers of a metallization level are limited in lateral extent to the viahole or plug extending through an insulating layer.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7622381 |
Semiconductor structure and the forming method thereof |
Nov. 24, 2009 |
| 7618888 |
Temperature-controlled metallic dry-fill process |
Nov. 17, 2009 |
| RE40983 |
Method to plate C4 to copper stud |
Nov. 17, 2009 |
| 7608535 |
Method for forming metal contact in semiconductor device |
Oct. 27, 2009 |
| 7605072 |
Interconnect structure with a barrier-redundancy feature |
Oct. 20, 2009 |
| 7605075 |
Multilayer circuit board and method of manufacturing the same |
Oct. 20, 2009 |
| 7605035 |
Method of fabricating semiconductor device by exposing upper sidewalls of contact plug to form charge storage electrode |
Oct. 20, 2009 |
| 7601630 |
Semiconductor device and method for fabricating the same |
Oct. 13, 2009 |
| 7601634 |
Process for producing a contact pad on a region of an integrated circuit, in particular on the electrodes of a transistor |
Oct. 13, 2009 |
| 7592703 |
RF and MMIC stackable micro-modules |
Sep. 22, 2009 |
| 7588960 |
Nanotube device structure and methods of fabrication |
Sep. 15, 2009 |
| 7589016 |
Method of depositing a sculptured copper seed layer |
Sep. 15, 2009 |
| 7585770 |
Method of growing carbon nanotubes and method of manufacturing field emission device having the same |
Sep. 8, 2009 |
| 7585723 |
Method for fabricating capacitor |
Sep. 8, 2009 |
| 7582558 |
Reducing corrosion in copper damascene processes |
Sep. 1, 2009 |
| 7569479 |
Method for fabricating semiconductor device |
Aug. 4, 2009 |
| 7566646 |
Three dimensional programmable device and method for fabricating the same |
Jul. 28, 2009 |
| 7566653 |
Interconnect structure with grain growth promotion layer and method for forming the same |
Jul. 28, 2009 |
| 7560307 |
Resin composition, heat-resistant resin paste and semiconductor device using these and method of preparing the same |
Jul. 14, 2009 |
| 7557450 |
Wiring substrate and electronic parts packaging structure |
Jul. 7, 2009 |
| 7544605 |
Method of making a contact on a backside of a die |
Jun. 9, 2009 |
| 7545045 |
Dummy via for reducing proximity effect and method of using the same |
Jun. 9, 2009 |
| 7541276 |
Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer |
Jun. 2, 2009 |
| 7541279 |
Method for manufacturing semiconductor device |
Jun. 2, 2009 |
| 7538027 |
Fabrication method for semiconductor interconnections |
May. 26, 2009 |
| 7538413 |
Semiconductor components having through interconnects |
May. 26, 2009 |
| 7534722 |
Back-to-front via process |
May. 19, 2009 |
| 7524756 |
Process of forming a semiconductor assembly having a contact structure and contact liner |
Apr. 28, 2009 |
| 7517792 |
Semiconductor device having a multilayer interconnection structure, fabrication method thereof, and designing method thereof |
Apr. 14, 2009 |
| 7514297 |
Methods for a multiple die integrated circuit package |
Apr. 7, 2009 |
| 7514353 |
Contact metallization scheme using a barrier layer over a silicide layer |
Apr. 7, 2009 |
| 7514354 |
Methods for forming damascene wiring structures having line and plug conductors formed from different materials |
Apr. 7, 2009 |
| 7510961 |
Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure |
Mar. 31, 2009 |
| 7504334 |
Semiconductor device and method for manufacturing same |
Mar. 17, 2009 |
| 7498258 |
Through-hole conductors for semiconductor substrates and method for making same |
Mar. 3, 2009 |
| 7498256 |
Copper contact via structure using hybrid barrier layer |
Mar. 3, 2009 |
| 7494917 |
Method for forming an electrical interconnection providing improved surface morphology of tungsten |
Feb. 24, 2009 |
| 7494919 |
Method for post lithographic critical dimension shrinking using thermal reflow process |
Feb. 24, 2009 |
| 7494920 |
Method of fabricating a vertically mountable IC package |
Feb. 24, 2009 |
| 7494925 |
Method for making through-hole conductors for semiconductor substrates |
Feb. 24, 2009 |
| 7494927 |
Method of growing electrical conductors |
Feb. 24, 2009 |
| 7482264 |
Method of forming metal line of semiconductor device, and semiconductor device |
Jan. 27, 2009 |
| 7476963 |
Three-dimensional stack manufacture for integrated circuit devices and method of manufacture |
Jan. 13, 2009 |
| 7473634 |
Method for integrated substrate processing in copper metallization |
Jan. 6, 2009 |
| 7473639 |
Method of forming dual damascene pattern |
Jan. 6, 2009 |
| 7468318 |
Method for manufacturing mold type semiconductor device |
Dec. 23, 2008 |
| 7465652 |
Method of forming a catalyst layer on the barrier layer of a conductive interconnect of a semiconductor device |
Dec. 16, 2008 |
| 7466027 |
Interconnect structures with surfaces roughness improving liner and methods for fabricating the same |
Dec. 16, 2008 |
| 7462523 |
Semiconductor memory device and method for manufacturing the same |
Dec. 9, 2008 |
| 7456094 |
LDMOS transistor |
Nov. 25, 2008 |
|
|
|
