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Class Information
Number: 438/626
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > At least one metallization level formed of diverse conductive layers > Planarization
Description: Processes wherein at least one of the metallization levels or at least one separating insulating layer is leveled into a single plane at any stage in the process.

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Patent Number Title Of Patent Date Issued
6750543 Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device Jun. 15, 2004
6743683 Polysilicon opening polish Jun. 1, 2004
6737346 Integrated circuit with modified metal features and method of fabrication therefor May. 18, 2004
6734097 Liner with poor step coverage to improve contact resistance in W contacts May. 11, 2004
6727172 Process to reduce chemical mechanical polishing damage of narrow copper lines Apr. 27, 2004
6723631 Fabrication method of semiconductor integrated circuit device Apr. 20, 2004
6723600 Method for making a metal-insulator-metal capacitor using plate-through mask techniques Apr. 20, 2004
6716771 Method for post-CMP conversion of a hydrophobic surface of a low-k dielectric layer to a hydrophilic surface Apr. 6, 2004
6716741 Method of patterning dielectric layer with low dielectric constant Apr. 6, 2004
6716743 Method of manufacturing a semiconductor device Apr. 6, 2004
6713385 Implanting ions in shallow trench isolation structures Mar. 30, 2004
6713235 Method for fabricating thin-film substrate and thin-film substrate fabricated by the method Mar. 30, 2004
6709874 Method of manufacturing a metal cap layer for preventing damascene conductive lines from oxidation Mar. 23, 2004
6709970 Method for creating a damascene interconnect using a two-step electroplating process Mar. 23, 2004
6706629 Barrier-free copper interconnect Mar. 16, 2004
6696358 Viscous protective overlayers for planarization of integrated circuits Feb. 24, 2004
6693028 Semiconductor device having multilayer wiring structure and method for manufacturing the same Feb. 17, 2004
6693029 Method of forming an insulative substrate having conductive filled vias Feb. 17, 2004
6692580 Method of cleaning a dual damascene structure Feb. 17, 2004
6686286 Method for forming a borderless contact of a semiconductor device Feb. 3, 2004
6673718 Methods for forming aluminum metal wirings Jan. 6, 2004
6670274 Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure Dec. 30, 2003
6664154 Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes Dec. 16, 2003
6660629 Chemical mechanical polishing method for fabricating copper damascene structure Dec. 9, 2003
6656834 Method of selectively alloying interconnect regions by deposition process Dec. 2, 2003
6656841 Method of forming multi layer conductive line in semiconductor device Dec. 2, 2003
6653732 Electronic component having a semiconductor chip Nov. 25, 2003
6649515 Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures Nov. 18, 2003
6649513 Copper back-end-of-line by electropolish Nov. 18, 2003
6645851 Method of forming planarized coatings on contact hole patterns of various duty ratios Nov. 11, 2003
6639285 Method for fabricating a semiconductor device Oct. 28, 2003
6638851 Dual hardmask single damascene integration scheme in an organic low k ILD Oct. 28, 2003
6638863 Electropolishing metal layers on wafers having trenches or vias with dummy structures Oct. 28, 2003
6635586 Method of forming a spin-on-glass insulation layer Oct. 21, 2003
6635562 Methods and solutions for cleaning polished aluminum-containing layers Oct. 21, 2003
6627539 Method of forming dual-damascene interconnect structures employing low-k dielectric materials Sep. 30, 2003
6617241 Method of thick film planarization Sep. 9, 2003
6613594 Surface plasmon resonance-based endpoint detection for chemical mechanical planarization (CMP) Sep. 2, 2003
6607955 Method of forming self-aligned contacts in a semiconductor device Aug. 19, 2003
6600229 Planarizers for spin etch planarization of electronic components Jul. 29, 2003
6596639 Method for chemical/mechanical planarization of a semiconductor wafer having dissimilar metal pattern densities Jul. 22, 2003
6593226 Method for adding features to a design layout and process for designing a mask Jul. 15, 2003
6593202 Semiconductor memory device and fabrication method thereof Jul. 15, 2003
6593236 Method of forming a metal wiring in a semiconductor device with copper seed Jul. 15, 2003
6593230 Method of manufacturing semiconductor device Jul. 15, 2003
6589863 Semiconductor device and manufacturing method thereof Jul. 8, 2003
6586327 Fabrication of semiconductor devices Jul. 1, 2003
6586326 Metal planarization system Jul. 1, 2003
6583050 Semiconductor wafer with improved flatness, and process for producing the semiconductor wafer Jun. 24, 2003
6583053 Use of a sacrificial layer to facilitate metallization for small features Jun. 24, 2003

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