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Class Information
Number: 438/626
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > At least one metallization level formed of diverse conductive layers > Planarization
Description: Processes wherein at least one of the metallization levels or at least one separating insulating layer is leveled into a single plane at any stage in the process.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6890830 Semiconductor device and method for fabricating the same May. 10, 2005
6887776 Methods to form metal lines using selective electrochemical deposition May. 3, 2005
6884713 Method for forming metal line of semiconductor device Apr. 26, 2005
6881660 Method for forming wiring structure Apr. 19, 2005
6869872 Method of manufacturing a semiconductor memory device having a metal contact structure Mar. 22, 2005
6867127 Diamond metal-filled patterns achieving low parasitic coupling capacitance Mar. 15, 2005
6864583 Wiring structure of semiconductor device Mar. 8, 2005
6861348 Pre-pattern surface modification of low-k dielectrics Mar. 1, 2005
6858549 Method for forming wiring structure Feb. 22, 2005
6858526 Methods of forming materials between conductive electrical components, and insulating materials Feb. 22, 2005
6858452 Method for isolating self-aligned contact pads Feb. 22, 2005
6849923 Semiconductor device and manufacturing method of the same Feb. 1, 2005
6849537 Method of suppressing void formation in a metal line Feb. 1, 2005
6846737 Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials Jan. 25, 2005
6841466 Method of selectively making copper using plating technology Jan. 11, 2005
6838772 Semiconductor device Jan. 4, 2005
6838371 Method of manufacturing semiconductor device Jan. 4, 2005
6835657 Method for recrystallizing metal in features of a semiconductor chip Dec. 28, 2004
6835648 Semiconductor PMD layer dielectric Dec. 28, 2004
6828226 Removal of SiON residue after CMP Dec. 7, 2004
6828227 Method for applying uniform pressurized film across wafer Dec. 7, 2004
6825109 Methods of fabricating buried digit lines Nov. 30, 2004
6821881 Method for chemical mechanical polishing of semiconductor substrates Nov. 23, 2004
6818548 Fast ramp anneal for hillock suppression in copper-containing structures Nov. 16, 2004
6818555 Method for metal etchback with self aligned etching mask Nov. 16, 2004
6815336 Planarization of copper damascene using reverse current electroplating and chemical mechanical polishing Nov. 9, 2004
6812076 Dual silicon layer for chemical mechanical polishing planarization Nov. 2, 2004
6812069 Method for improving semiconductor process wafer CMP uniformity while avoiding fracture Nov. 2, 2004
6812128 Method of manufacturing multilayer structured semiconductor device Nov. 2, 2004
6797557 Methods and systems for forming embedded DRAM for an MIM capacitor Sep. 28, 2004
6797983 Method of fabrication LCOS structure Sep. 28, 2004
6794756 Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines Sep. 21, 2004
6794691 Use of irregularly shaped conductive filler features to improve planarization of the conductive layer while reducing parasitic capacitance introduced by the filler features Sep. 21, 2004
6794286 Process for fabricating a metal wiring and metal contact in a semicondutor device Sep. 21, 2004
6790710 Method of manufacturing an integrated circuit package Sep. 14, 2004
6787466 High throughout process for the formation of a refractory metal nucleation layer Sep. 7, 2004
6784091 Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices Aug. 31, 2004
6784093 Copper surface passivation during semiconductor manufacturing Aug. 31, 2004
6782512 Fabrication method for a semiconductor device with dummy patterns Aug. 24, 2004
6770536 Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate Aug. 3, 2004
6770495 Method for revealing active regions in a SOI structure for DUT backside inspection Aug. 3, 2004
6764950 Fabrication method for semiconductor integrated circuit device Jul. 20, 2004
6759323 Method for filling depressions in a surface of a semiconductor structure, and a semiconductor structure filled in this way Jul. 6, 2004
6759297 Low temperature deposition of dielectric materials in magnetoresistive random access memory devices Jul. 6, 2004
6759322 Method for forming wiring structure Jul. 6, 2004
6759332 Method for producing dual damascene interconnections and structure produced thereby Jul. 6, 2004
6756307 Apparatus for electrically planarizing semiconductor wafers Jun. 29, 2004
6756309 Feed forward process control method for adjusting metal line Rs Jun. 29, 2004
6750139 Dummy metal pattern method and apparatus Jun. 15, 2004
6750543 Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device Jun. 15, 2004

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