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Class Information
Number: 438/626
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > At least one metallization level formed of diverse conductive layers > Planarization
Description: Processes wherein at least one of the metallization levels or at least one separating insulating layer is leveled into a single plane at any stage in the process.










Patents under this class:
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Patent Number Title Of Patent Date Issued
7172962 Method of manufacturing a semiconductor device Feb. 6, 2007
7169695 Method for forming a dual damascene structure Jan. 30, 2007
7166506 Poly open polish process Jan. 23, 2007
7163780 Electronic device manufacture Jan. 16, 2007
7157368 Method of accelerating test of semiconductor device Jan. 2, 2007
7144816 Polysilicon opening polish Dec. 5, 2006
7144808 Integration flow to prevent delamination from copper Dec. 5, 2006
7135400 Damascene process capable of avoiding via resist poisoning Nov. 14, 2006
7119008 Integrating metal layers with ultra low-K dielectrics Oct. 10, 2006
7112527 Manufacturing method for short distance wiring layers and long distance wiring layers in a semiconductor device Sep. 26, 2006
7104869 Barrier removal at low polish pressure Sep. 12, 2006
7105914 Integrated circuit and seed layers Sep. 12, 2006
7101727 Passivation planarization Sep. 5, 2006
7094679 Carbon nanotube interconnect Aug. 22, 2006
7084503 Semiconductor device and fabricating method thereof Aug. 1, 2006
7084053 Unidirectionally conductive materials for interconnection Aug. 1, 2006
7074709 Localized doping and/or alloying of metallization for increased interconnect performance Jul. 11, 2006
7074710 Method of wafer patterning for reducing edge exclusion zone Jul. 11, 2006
7071099 Forming of local and global wiring for semiconductor product Jul. 4, 2006
7060619 Reduction of the shear stress in copper via's in organic interlayer dielectric material Jun. 13, 2006
7060606 Method and apparatus for chemical mechanical polishing of semiconductor substrates Jun. 13, 2006
7056823 Backend metallization method and device obtained therefrom Jun. 6, 2006
7026234 Parasitic capacitance-preventing dummy solder bump structure and method of making the same Apr. 11, 2006
7015133 Dual damascene structure formed of low-k dielectric materials Mar. 21, 2006
7012335 Semiconductor device wiring and method of manufacturing the same Mar. 14, 2006
7008870 Structure applied to a photolithographic process and method for fabricating a semiconductor device Mar. 7, 2006
7005378 Processes for fabricating conductive patterns using nanolithography as a patterning tool Feb. 28, 2006
6997776 Process for producing a semiconductor wafer Feb. 14, 2006
6992024 Gapfill process using a combination of spin-on-glass deposition and chemical vapor deposition techniques Jan. 31, 2006
6987028 Method of fabricating a microelectronic die Jan. 17, 2006
6984581 Structural reinforcement of highly porous low k dielectric films by ILD posts Jan. 10, 2006
6972492 Method and structure to form capacitor in copper damascene process for integrated circuit devices Dec. 6, 2005
6967155 Adhesion of copper and etch stop layer for copper alloy Nov. 22, 2005
6964919 Low-k dielectric film with good mechanical strength Nov. 15, 2005
6962872 High density chip carrier with integrated passive devices Nov. 8, 2005
6960500 Semiconductor device and method of manufacturing the same including forming metal silicide gate lines and source lines Nov. 1, 2005
6951808 Metal planarization system Oct. 4, 2005
6951807 Semiconductor device and manufacturing method thereof Oct. 4, 2005
6949480 Method for depositing silicon nitride layer of semiconductor device Sep. 27, 2005
6946384 Stacked device underfill and a method of fabrication Sep. 20, 2005
6939795 Selective dry etching of tantalum and tantalum nitride Sep. 6, 2005
6939796 System, method and apparatus for improved global dual-damascene planarization Sep. 6, 2005
6936534 Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallization Aug. 30, 2005
6924225 Method for producing an electrically conductive contact Aug. 2, 2005
6919266 Copper technology for ULSI metallization Jul. 19, 2005
6919267 Method for forming wiring structure Jul. 19, 2005
6916737 Methods of manufacturing a semiconductor device Jul. 12, 2005
6905967 Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems Jun. 14, 2005
6903004 Method of making a semiconductor device having a low K dielectric Jun. 7, 2005
6903020 Method of forming buried wiring in semiconductor device Jun. 7, 2005

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