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Class Information
Number: 438/626
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > At least one metallization level formed of diverse conductive layers > Planarization
Description: Processes wherein at least one of the metallization levels or at least one separating insulating layer is leveled into a single plane at any stage in the process.
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7968462 |
Noble metal activation layer |
Jun. 28, 2011 |
| 7951707 |
Etching method for semiconductor element |
May. 31, 2011 |
| 7951706 |
Method of manufacturing metal interconnection |
May. 31, 2011 |
| 7939446 |
Process for reversing tone of patterns on integerated circuit and structural process for nanoscale fabrication |
May. 10, 2011 |
| 7927990 |
Forming complimentary metal features using conformal insulator layer |
Apr. 19, 2011 |
| 7928003 |
Air gap interconnects using carbon-based films |
Apr. 19, 2011 |
| 7906430 |
Method of manufacturing a semiconductor device with a peeling prevention layer |
Mar. 15, 2011 |
| 7880293 |
Wafer integrated with permanent carrier and method therefor |
Feb. 1, 2011 |
| 7875547 |
Contact hole structures and contact structures and fabrication methods thereof |
Jan. 25, 2011 |
| 7871921 |
Methods of forming interconnection structures for semiconductor devices |
Jan. 18, 2011 |
| 7871923 |
Self-aligned air-gap in interconnect structures |
Jan. 18, 2011 |
| 7863173 |
Variable resistance non-volatile memory cells and methods of fabricating same |
Jan. 4, 2011 |
| 7858513 |
Fabrication of self-aligned via holes in polymer thin films |
Dec. 28, 2010 |
| 7846839 |
Film forming method, semiconductor device manufacturing method, semiconductor device, program and recording medium |
Dec. 7, 2010 |
| 7842601 |
Method of forming small pitch pattern using double spacers |
Nov. 30, 2010 |
| 7842602 |
Semiconductor device having silicon-diffused metal wiring layer and its manufacturing method |
Nov. 30, 2010 |
| 7838921 |
Memory cell arrangements |
Nov. 23, 2010 |
| 7829454 |
Method for integrating selective ruthenium deposition into manufacturing of a semiconductior device |
Nov. 9, 2010 |
| 7825026 |
Method for processing copper surface, method for forming copper pattern wiring and semiconductor device manufactured using such method |
Nov. 2, 2010 |
| 7825023 |
Method of manufacturing an interconnection structure |
Nov. 2, 2010 |
| 7820544 |
Method for forming metal wiring of semiconductor device and a semiconductor device manufactured by the same |
Oct. 26, 2010 |
| RE41842 |
Methods of forming electrical interconnects on integrated circuit substrates using selective slurries |
Oct. 19, 2010 |
| 7811927 |
Method of manufacturing metal line |
Oct. 12, 2010 |
| 7811930 |
Manufacturing method of dual damascene structure |
Oct. 12, 2010 |
| 7795131 |
Method of fabricating metal interconnects and inter-metal dielectric layer thereof |
Sep. 14, 2010 |
| RE41697 |
Method of forming planarized coatings on contact hole patterns of various duty ratios |
Sep. 14, 2010 |
| 7795061 |
Method of creating MEMS device cavities by a non-etching process |
Sep. 14, 2010 |
| 7790607 |
Method for reducing dielectric overetch using a dielectric etch stop at a planar surface |
Sep. 7, 2010 |
| 7790604 |
Krypton sputtering of thin tungsten layer for integrated circuits |
Sep. 7, 2010 |
| 7776683 |
Integrated circuit fabrication |
Aug. 17, 2010 |
| 7771779 |
Planarized microelectronic substrates |
Aug. 10, 2010 |
| 7745327 |
Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime |
Jun. 29, 2010 |
| 7745326 |
Semiconductor device having multiple wiring layers and method of producing the same |
Jun. 29, 2010 |
| 7737038 |
Method of fabricating semiconductor device including planarizing conductive layer using parameters of pattern density and depth of trenches |
Jun. 15, 2010 |
| 7718545 |
Fabrication process |
May. 18, 2010 |
| 7718522 |
Method and apparatus for plating a semiconductor package |
May. 18, 2010 |
| 7704856 |
Semiconductor device, wiring substrate forming method, and substrate processing apparatus |
Apr. 27, 2010 |
| 7704872 |
Ultraviolet assisted pore sealing of porous low k dielectric films |
Apr. 27, 2010 |
| 7700477 |
Method for fabricating semiconductor device |
Apr. 20, 2010 |
| 7696085 |
Dual damascene metal interconnect structure having a self-aligned via |
Apr. 13, 2010 |
| 7678684 |
Semiconductor integrated circuit device |
Mar. 16, 2010 |
| 7670915 |
Contact liner in integrated circuit technology |
Mar. 2, 2010 |
| 7662672 |
Manufacturing process of leadframe-based BGA packages |
Feb. 16, 2010 |
| 7662711 |
Method of forming dual damascene pattern |
Feb. 16, 2010 |
| 7663240 |
Semiconductor device with multiple interconnect layers and vias |
Feb. 16, 2010 |
| 7655539 |
Dice by grind for back surface metallized dies |
Feb. 2, 2010 |
| 7655556 |
Interconnect structures for semiconductor devices |
Feb. 2, 2010 |
| 7648898 |
Method to fabricate gate electrodes |
Jan. 19, 2010 |
| 7638430 |
Method of forming contact plug of semiconductor device |
Dec. 29, 2009 |
| 7638434 |
Method for filling a trench in a semiconductor product |
Dec. 29, 2009 |
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