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Class Information
Number: 438/626
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > At least one metallization level formed of diverse conductive layers > Planarization
Description: Processes wherein at least one of the metallization levels or at least one separating insulating layer is leveled into a single plane at any stage in the process.

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Patent Number Title Of Patent Date Issued
5679605 Multilevel interconnect structure of an integrated circuit formed by a single via etch and dual fill process Oct. 21, 1997
5674781 Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application Oct. 7, 1997
5670019 Removal process for tungsten etchback precipitates Sep. 23, 1997
5670409 Method of fabricating a semiconductor IC DRAM device enjoying enhanced focus margin Sep. 23, 1997
5670425 Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench Sep. 23, 1997
5663102 Method for forming multi-layered metal wiring semiconductor element using cmp or etch back Sep. 2, 1997
5663108 Optimized metal pillar via process Sep. 2, 1997
5658425 Method of etching contact openings with reduced removal rate of underlying electrically conductive titanium silicide layer Aug. 19, 1997
5656556 Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures Aug. 12, 1997
5641712 Method and structure for reducing capacitance between interconnect lines Jun. 24, 1997
5618752 Method of fabrication of surface mountable integrated circuits Apr. 8, 1997
5616519 Non-etch back SOG process for hot aluminum metallizations Apr. 1, 1997
5610099 Process for fabricating transistors using composite nitride structure Mar. 11, 1997
5604155 Al-based contact formation process using Ti glue layer to prevent nodule-induced bridging Feb. 18, 1997
5599740 Deposit-etch-deposit ozone/teos insulator layer method Feb. 4, 1997
5595937 Method for fabricating semiconductor device with interconnections buried in trenches Jan. 21, 1997
5593919 Process for forming a semiconductor device including conductive members Jan. 14, 1997
5585308 Method for improved pre-metal planarization Dec. 17, 1996
5571751 Interconnect structures for integrated circuits Nov. 5, 1996
5529955 Wiring forming method Jun. 25, 1996
5518963 Method for forming metal interconnection of semiconductor device May. 21, 1996
5512514 Self-aligned via and contact interconnect manufacturing method Apr. 30, 1996
5512512 Contact hole filling in a semiconductor device by irradiation with plasma of inert gas ions Apr. 30, 1996
5496773 Semiconductor processing method of providing an electrically conductive interconnecting plug between an elevationally inner electrically conductive node and an elevationally outer electrically Mar. 5, 1996
5491108 Method of producing semiconductor integrated circuit device having interplayer insulating film covering substrate Feb. 13, 1996
5488013 Method of forming transverse diffusion barrier interconnect structure Jan. 30, 1996
5480837 Process of making an integrated circuit having a planar conductive layer Jan. 2, 1996
5472912 Method of making an integrated circuit structure by using a non-conductive plug Dec. 5, 1995
5457059 Method for forming TiW fuses in high performance BiCMOS process Oct. 10, 1995
5451551 Multilevel metallization process using polishing Sep. 19, 1995
5436199 Pillar alignment and formation process Jul. 25, 1995
5420068 Semiconductor integrated circuit and a method for manufacturing a fully planar multilayer wiring structure May. 30, 1995
5420075 Forming multi-layered interconnections with fluorine compound treatment permitting selective deposition of insulator May. 30, 1995
5374591 Method of making a metal plug Dec. 20, 1994
5332694 Process for manufacturing a semiconductor device Jul. 26, 1994
5318916 Symmetric self-aligned processing Jun. 7, 1994
5305519 Multilevel interconnect structure and method of manufacturing the same Apr. 26, 1994
5288664 Method of forming wiring of semiconductor device Feb. 22, 1994
5286675 Blanket tungsten etchback process using disposable spin-on-glass Feb. 15, 1994
5275963 Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconductor chips and structures resulting therefrom Jan. 4, 1994
5272117 Method for planarizing a layer of material Dec. 21, 1993
5272115 Method of leveling the laminated surface of a semiconductor substrate Dec. 21, 1993
5250465 Method of manufacturing semiconductor devices Oct. 5, 1993
5200030 Method for manufacturing a planarized metal layer for semiconductor device Apr. 6, 1993
5187119 Multichip module and integrated circuit substrates having planarized patterned surfaces Feb. 16, 1993
5110762 Manufacturing a wiring formed inside a semiconductor device May. 5, 1992
5091340 Method for forming multilayer wirings on a semiconductor device Feb. 25, 1992
5084406 Method for forming low resistance DRAM digit-line Jan. 28, 1992
5063175 Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material Nov. 5, 1991
5006484 Making a semiconductor device with contact holes having different depths Apr. 9, 1991

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