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Class Information
Number: 438/626
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > At least one metallization level formed of diverse conductive layers > Planarization
Description: Processes wherein at least one of the metallization levels or at least one separating insulating layer is leveled into a single plane at any stage in the process.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6083826 Method for manufacturing semiconductor device capable of improving planarization Jul. 4, 2000
6083798 Method of producing a metal oxide semiconductor device with raised source/drain Jul. 4, 2000
6083835 Self-passivation of copper damascene Jul. 4, 2000
6080656 Method for forming a self-aligned copper structure with improved planarity Jun. 27, 2000
6080655 Method for fabricating conductive components in microelectronic devices and substrate structures thereof Jun. 27, 2000
6080653 Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component Jun. 27, 2000
6074941 Method of forming a via with plasma treatment of SOG Jun. 13, 2000
6063702 Global planarization method for inter level dielectric layers using IDL blocks May. 16, 2000
6060386 Method and apparatus for forming features in holes, trenches and other voids in the manufacturing of microelectronic devices May. 9, 2000
6060385 Method of making an interconnect structure May. 9, 2000
6060387 Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions May. 9, 2000
6060349 Planarization on an embedded dynamic random access memory May. 9, 2000
6057227 Oxide etch stop techniques for uniform damascene trench depth May. 2, 2000
6054378 Method for encapsulating a metal via in damascene Apr. 25, 2000
6054380 Method and apparatus for integrating low dielectric constant materials into a multilevel metallization and interconnect structure Apr. 25, 2000
6051496 Use of stop layer for chemical mechanical polishing of CU damascene Apr. 18, 2000
6048795 Process of fabricating a semiconductor device having nitrogen-containing silicon layer and refractory metal layer Apr. 11, 2000
6046108 Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby Apr. 4, 2000
6046104 Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias Apr. 4, 2000
6046098 Process of forming metal silicide interconnects Apr. 4, 2000
6043165 Methods of forming electrically interconnected lines using ultraviolet radiation as an organic compound cleaning agent Mar. 28, 2000
6043146 Process for forming a semiconductor device Mar. 28, 2000
6037253 Method for increasing interconnect packing density in integrated circuits Mar. 14, 2000
6037251 Process for intermetal SOG/SOP dielectric planarization Mar. 14, 2000
6033975 Implant screen and method Mar. 7, 2000
6030891 Vacuum baked HSQ gap fill layer for high integrity borderless vias Feb. 29, 2000
6027998 Method for fully planarized conductive line for a stack gate Feb. 22, 2000
6025259 Dual damascene process using high selectivity boundary layers Feb. 15, 2000
6025263 Underlayer process for high O.sub.3 /TEOS interlayer dielectric deposition Feb. 15, 2000
6025270 Planarization process using tailored etchback and CMP Feb. 15, 2000
6020255 Dual damascene interconnect process with borderless contact Feb. 1, 2000
6020257 Membrane dielectric isolation IC fabrication Feb. 1, 2000
6020256 Method of integrated circuit fabrication Feb. 1, 2000
6017815 Method of fabricating a border-less via Jan. 25, 2000
6010958 Method for improving the planarization of dielectric layer in the fabrication of metallic interconnects Jan. 4, 2000
6001726 Method for using a conductive tungsten nitride etch stop layer to form conductive interconnects and tungsten nitride contact structure Dec. 14, 1999
5989945 Thin film device provided with coating film, liquid crystal panel and electronic device, and method for making the thin film device Nov. 23, 1999
5980979 Method for consistently forming low resistance contact structures involving the removal of adhesion layer particles blocking via openings Nov. 9, 1999
5970375 Semiconductor fabrication employing a local interconnect Oct. 19, 1999
5970238 Method and apparatus for generating planarizing pattern and semiconductor integrated circuit device Oct. 19, 1999
5960314 Semiconductor processing method of providing an electrically conductive interconnecting plug between an elevationally conductive node and an elevationally outer electrically conductive node Sep. 28, 1999
5960317 Methods of forming electrical interconnects on integrated circuit substrates using selective slurries Sep. 28, 1999
5956618 Process for producing multi-level metallization in an integrated circuit Sep. 21, 1999
5953635 Interlayer dielectric with a composite dielectric stack Sep. 14, 1999
5937324 Method for forming a line-on-line multi-level metal interconnect structure for use in integrated circuits Aug. 10, 1999
5937322 Semiconductor manufacturing process with oxide film formed on an uneven surface pattern Aug. 10, 1999
5928960 Process for reducing pattern factor effects in CMP planarization Jul. 27, 1999
5924007 Method for improving the planarization of inter-poly dielectric Jul. 13, 1999
5924006 Trench surrounded metal pattern Jul. 13, 1999
5913142 Method of improving the planarizaton of an inter-metal dielectric layer Jun. 15, 1999

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