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Class Information
Number: 438/626
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > At least one metallization level formed of diverse conductive layers > Planarization
Description: Processes wherein at least one of the metallization levels or at least one separating insulating layer is leveled into a single plane at any stage in the process.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6214745 Method of improving surface planarity of chemical-mechanical polishing operation by forming shallow dummy pattern Apr. 10, 2001
6211060 Method for planarizing a damascene structure Apr. 3, 2001
6211064 Method for fabricating CMOS device Apr. 3, 2001
6211084 Method of forming reliable copper interconnects Apr. 3, 2001
6207546 Prevent passivation from keyhole damage and resist extrusion by a crosslinking mechanism Mar. 27, 2001
6207222 Dual damascene metallization Mar. 27, 2001
6204107 Method for forming multi-layered liner on sidewall of node contact opening Mar. 20, 2001
6204169 Processing for polishing dissimilar conductive layers in a semiconductor device Mar. 20, 2001
6194296 Method for making planarized polycide Feb. 27, 2001
6194307 Elimination of copper line damages for damascene process Feb. 27, 2001
6194316 Method for forming CU-thin film Feb. 27, 2001
6191048 Process for manufacturing composite glass/Si substrates for microwave integrated circuit fabrication Feb. 20, 2001
6187683 Method for final passivation of integrated circuit Feb. 13, 2001
6184124 Method of making embedded wiring system Feb. 6, 2001
6184105 Method for post transistor isolation Feb. 6, 2001
6180511 Method for forming intermetal dielectric of semiconductor device Jan. 30, 2001
6180510 Method of manufacturing a substantially flat surface of a semiconductor device through a polishing operation Jan. 30, 2001
6180508 Methods of fabricating buried digit lines and semiconductor devices including same Jan. 30, 2001
6177337 Method of reducing metal voids in semiconductor device interconnection Jan. 23, 2001
6171928 Method of fabricating shallow trench insolation Jan. 9, 2001
6165889 Process for forming trenches and contacts during the formation of a semiconductor memory device Dec. 26, 2000
6162722 Unlanded via process Dec. 19, 2000
6159843 Method of fabricating landing pad Dec. 12, 2000
6156651 Metallization method for porous dielectrics Dec. 5, 2000
6156637 Method of planarizing a semiconductor device by depositing a dielectric ply structure Dec. 5, 2000
6150260 Sacrificial stop layer and endpoint for metal CMP Nov. 21, 2000
6146995 Method for manufacturing interconnecting plug Nov. 14, 2000
6146997 Method for forming self-aligned contact hole Nov. 14, 2000
6147000 Method for forming low dielectric passivation of copper interconnects Nov. 14, 2000
6143657 Method of increasing the stability of a copper to copper interconnection process and structure manufactured thereby Nov. 7, 2000
6140222 Integrated circuit dielectric formation Oct. 31, 2000
6136689 Method of forming a micro solder ball for use in C4 bonding process Oct. 24, 2000
6133133 Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component Oct. 17, 2000
6130158 Filling connection hole with wiring material by using centrifugal force Oct. 10, 2000
6130151 Method of manufacturing air gap in multilevel interconnection Oct. 10, 2000
6127259 Phosphoric acid process for removal of contact BARC layer Oct. 3, 2000
6124198 Ultra high-speed chip interconnect using free-space dielectrics Sep. 26, 2000
6117766 Method of forming contact plugs in a semiconductor device Sep. 12, 2000
6117763 Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water Sep. 12, 2000
6114234 Method of making a semiconductor with copper passivating film Sep. 5, 2000
6107185 Conductive material adhesion enhancement in damascene process for semiconductors Aug. 22, 2000
6103618 Method for forming an interconnection in a semiconductor element Aug. 15, 2000
6103557 Semiconductor device or thin-film transistor manufacturing apparatus and manufacturing method Aug. 15, 2000
6100185 Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line Aug. 8, 2000
6100180 Formation of a self-aligned integrated circuit structure using planarization to form a top surface Aug. 8, 2000
6100181 Low dielectric constant coating of conductive material in a damascene process for semiconductors Aug. 8, 2000
6096634 Method of patterning a submicron semiconductor layer Aug. 1, 2000
6093637 Method of making a multi-layer interconnection structure Jul. 25, 2000
6093635 High integrity borderless vias with HSQ gap filled patterned conductive layers Jul. 25, 2000
6087250 Semiconductor device having multilayered metal interconnection structure and manufacturing method thereof Jul. 11, 2000

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