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Class Information
Number: 438/626
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > At least one metallization level formed of diverse conductive layers > Planarization
Description: Processes wherein at least one of the metallization levels or at least one separating insulating layer is leveled into a single plane at any stage in the process.










Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Patent Number Title Of Patent Date Issued
6340601 Method for reworking copper metallurgy in semiconductor devices Jan. 22, 2002
6340636 Method for forming metal line in semiconductor device Jan. 22, 2002
6335274 Method for forming a high-RI oxide film to reduce fluorine diffusion in HDP FSG process Jan. 1, 2002
6335257 Method of making pillar-type structure on semiconductor substrate Jan. 1, 2002
6333257 Interconnection structure and method for forming the same Dec. 25, 2001
6333221 Method for improving planarization of an ILD layer Dec. 25, 2001
6331481 Damascene etchback for low .epsilon. dielectric Dec. 18, 2001
6329280 Interim oxidation of silsesquioxane dielectric for dual damascene process Dec. 11, 2001
6326320 Method for forming oxide layer on conductor plug of trench structure Dec. 4, 2001
6326293 Formation of recessed polysilicon plugs using chemical-mechanical-polishing (CMP) and selective oxidation Dec. 4, 2001
6323113 Intelligent gate-level fill methods for reducing global pattern density effects Nov. 27, 2001
6319768 Method for fabricating capacitor in dram cell Nov. 20, 2001
6313025 Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit Nov. 6, 2001
6312991 Elimination of poly cap easy poly 1 contact for NAND product Nov. 6, 2001
6309959 Formation of self-aligned passivation for interconnect to minimize electromigration Oct. 30, 2001
6303431 Method of fabricating bit lines Oct. 16, 2001
6303505 Copper interconnect with improved electromigration resistance Oct. 16, 2001
6291367 Method for depositing a selected thickness of an interlevel dielectric material to achieve optimum global planarity on a semiconductor wafer Sep. 18, 2001
6291335 Locally folded split level bitline wiring Sep. 18, 2001
6287956 Multilevel interconnecting structure in semiconductor device and method of forming the same Sep. 11, 2001
6284647 Method to improve the uniformity of chemical mechanical polishing Sep. 4, 2001
6284574 Method of producing heat dissipating structure for semiconductor devices Sep. 4, 2001
6284641 Method of forming a contact using a sacrificial spacer Sep. 4, 2001
6277754 Method of planarizing dielectric layer Aug. 21, 2001
6274476 Semiconductor device and method of manufacturing the same Aug. 14, 2001
6274478 Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process Aug. 14, 2001
6274480 Method of Fabricating semiconductor device Aug. 14, 2001
6271124 Method of making a dynamic random access memory device utilizing chemical mechanical polishing Aug. 7, 2001
6265298 Method for forming inter-metal dielectrics Jul. 24, 2001
6265305 Method of preventing corrosion of a titanium layer in a semiconductor wafer Jul. 24, 2001
6265315 Method for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuits Jul. 24, 2001
6260266 Method of forming wire interconnection wire Jul. 17, 2001
6261950 Self-aligned metal caps for interlevel metal connections Jul. 17, 2001
6261944 Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect Jul. 17, 2001
6258466 Metallization on titanium aluminide Jul. 10, 2001
6258712 Method for forming a borderless contact Jul. 10, 2001
6255211 Silicon carbide stop layer in chemical mechanical polishing over metallization layers Jul. 3, 2001
6251772 Dielectric adhesion enhancement in damascene process for semiconductors Jun. 26, 2001
6251771 Hydrogen passivation of chemical-mechanically polished copper-containing layers Jun. 26, 2001
6245667 Method of forming via Jun. 12, 2001
6242341 Planarization using laser ablation Jun. 5, 2001
6239020 Method for forming interlayer dielectric layer May. 29, 2001
6239021 Dual barrier and conductor deposition in a dual damascene process for semiconductors May. 29, 2001
6232174 Methods for fabricating a semiconductor memory device including flattening of a capacitor dielectric film May. 15, 2001
6228759 Method of forming an alloy precipitate to surround interconnect to minimize electromigration May. 8, 2001
6228707 Semiconductor arrangement having capacitive structure and manufacture thereof May. 8, 2001
6225209 Method of fabricating crack resistant inter-layer dielectric for a salicide process May. 1, 2001
6221754 Method of fabricating a plug Apr. 24, 2001
6221758 Effective diffusion barrier process and device manufactured thereby Apr. 24, 2001
6218290 Copper dendrite prevention by chemical removal of dielectric Apr. 17, 2001

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