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Class Information
Number: 438/623
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Including organic insulating material between metal levels
Description: Processes wherein the intervening dielectric is at least partly composed of organic insulating material.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6908844 Metallization arrangement for semiconductor structure and corresponding fabrication method Jun. 21, 2005
6908846 Method and apparatus for detecting endpoint during plasma etching of thin films Jun. 21, 2005
6904675 Method of forming electrical interconnects having electromigration-inhibiting plugs Jun. 14, 2005
6903004 Method of making a semiconductor device having a low K dielectric Jun. 7, 2005
6903002 Low-k dielectric layer with air gaps Jun. 7, 2005
6898851 Electronic device manufacturing method May. 31, 2005
6890847 Polynorbornene foam insulation for integrated circuits May. 10, 2005
6881662 Pattern formation process for an integrated circuit substrate Apr. 19, 2005
6878616 Low-k dielectric material system for IC application Apr. 12, 2005
6875704 Method for forming pattern using printing process Apr. 5, 2005
6875687 Capping layer for extreme low dielectric constant films Apr. 5, 2005
6875682 Mesh pad structure to eliminate IMD crack on pad Apr. 5, 2005
6872652 Method of cleaning an inter-level dielectric interconnect Mar. 29, 2005
6867125 Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material Mar. 15, 2005
6867126 Method to increase cracking threshold for low-k materials Mar. 15, 2005
6867121 Method of apparatus for interconnecting a relatively fine pitch circuit layer and adjacent power plane(s) in a laminated construction Mar. 15, 2005
6864583 Wiring structure of semiconductor device Mar. 8, 2005
6864580 Semiconductor device and method of manufacturing the same Mar. 8, 2005
6861744 Multilayer ceramic substrate utilizing an intaglio plate with a plurality of grooves having different depths Mar. 1, 2005
6861284 Semiconductor device and production method thereof Mar. 1, 2005
6855625 Manufacturing method of multilayer substrate Feb. 15, 2005
6855626 Wiring substrate having position information Feb. 15, 2005
6852648 Semiconductor device having a low dielectric constant dielectric material and process for its manufacture Feb. 8, 2005
6852616 Semiconductor device and method for producing the same Feb. 8, 2005
6844255 Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry Jan. 18, 2005
6841463 Interlevel dielectric structure and method of forming same Jan. 11, 2005
6841467 Method for producing semiconductor device Jan. 11, 2005
6838370 Method of manufacturing semiconductor device and manufacturing apparatus Jan. 4, 2005
6838772 Semiconductor device Jan. 4, 2005
6835645 Method for fabricating semiconductor device Dec. 28, 2004
6835647 Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method Dec. 28, 2004
6833319 Method for fabricating semiconductor device Dec. 21, 2004
6833300 Method of forming integrated circuit contacts Dec. 21, 2004
6830999 Method of fabricating flip chip semiconductor device utilizing polymer layer for reducing thermal expansion coefficient differential Dec. 14, 2004
6828683 Semiconductor devices, and semiconductor processing methods Dec. 7, 2004
6828258 Method of forming an insulating film having SI-C, SI-O and SI-H bonds to cover wiringlines of a semiconductor device Dec. 7, 2004
6825060 Photosensitive polymeric memory elements Nov. 30, 2004
6818552 Method for eliminating reaction between photoresist and OSG Nov. 16, 2004
6818540 Fine pitch system and method for reinforcing bond pads in semiconductor devices Nov. 16, 2004
6815334 Method for forming multi-layer metal line of semiconductor device Nov. 9, 2004
6815333 Tri-layer masking architecture for patterning dual damascene interconnects Nov. 9, 2004
6815332 Method for forming integrated dielectric layers Nov. 9, 2004
6815331 Method for forming metal wiring layer of semiconductor device Nov. 9, 2004
6815346 Unique feature design enabling structural integrity for advanced low k semiconductor chips Nov. 9, 2004
6812133 Fabrication method of semiconductor device Nov. 2, 2004
6812135 Adhesion enhancement between CVD dielectric and spin-on low-k silicate films Nov. 2, 2004
6812132 Filling small dimension vias using supercritical carbon dioxide Nov. 2, 2004
6812131 Use of sacrificial inorganic dielectrics for dual damascene processes utilizing organic intermetal dielectrics Nov. 2, 2004
6812130 Self-aligned dual damascene etch using a polymer Nov. 2, 2004
6812128 Method of manufacturing multilayer structured semiconductor device Nov. 2, 2004

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