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Class Information
Number: 438/623
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Including organic insulating material between metal levels
Description: Processes wherein the intervening dielectric is at least partly composed of organic insulating material.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6153518 Method of making chip size package substrate Nov. 28, 2000
6153511 Semiconductor device having a multilayered interconnection structure Nov. 28, 2000
6153521 Metallized interconnection structure and method of making the same Nov. 28, 2000
6153525 Methods for chemical mechanical polish of organic polymer dielectric films Nov. 28, 2000
6150258 Plasma deposited fluorinated amorphous carbon films Nov. 21, 2000
6150274 Method of enhancing CMP removal rate of polymer-like material and improving planarization in integrated circuit structure Nov. 21, 2000
6150252 Multi-stage semiconductor cavity filling process Nov. 21, 2000
6146985 Low capacitance interconnection Nov. 14, 2000
6146992 Vertically integrated semiconductor component and method of producing the same Nov. 14, 2000
6143638 Passivation structure and its method of fabrication Nov. 7, 2000
6143670 Method to improve adhesion between low dielectric constant layer and silicon containing dielectric layer Nov. 7, 2000
6140225 Method of manufacturing semiconductor device having multilayer wiring Oct. 31, 2000
6140222 Integrated circuit dielectric formation Oct. 31, 2000
6136624 Array substrate, liquid crystal display device and their manufacturing method Oct. 24, 2000
6133137 Semiconductor device and method of manufacturing the same Oct. 17, 2000
6133138 Method of manufacturing semiconductor device having multilayer interconnection structure Oct. 17, 2000
6130152 Aerogel thin film formation from multi-solvent systems Oct. 10, 2000
6124641 Semiconductor device organic insulator film Sep. 26, 2000
6121130 Laser curing of spin-on dielectric thin films Sep. 19, 2000
6117763 Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water Sep. 12, 2000
6117764 Use of a plasma source to form a layer during the formation of a semiconductor device Sep. 12, 2000
6114233 Dual damascene process using low-dielectric constant materials Sep. 5, 2000
6114259 Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage Sep. 5, 2000
6114186 Hydrogen silsesquioxane thin films for low capacitance structures in integrated circuits Sep. 5, 2000
6114236 Process for production of semiconductor device having an insulating film of low dielectric constant Sep. 5, 2000
6107184 Nano-porous copolymer films having low dielectric constants Aug. 22, 2000
6107183 Method of forming an interlevel dielectric Aug. 22, 2000
6100184 Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer Aug. 8, 2000
6100587 Silicon carbide barrier layers for porous low dielectric constant materials Aug. 8, 2000
6096648 Copper/low dielectric interconnect formation with reduced electromigration Aug. 1, 2000
6093633 Method of making a semiconductor device Jul. 25, 2000
6093636 Process for manufacture of integrated circuit device using a matrix comprising porous high temperature thermosets Jul. 25, 2000
6093635 High integrity borderless vias with HSQ gap filled patterned conductive layers Jul. 25, 2000
6090698 Fabrication method for an insulation structure having a low dielectric constant Jul. 18, 2000
6083821 Integrated circuit having a void between adjacent conductive lines Jul. 4, 2000
6083850 HSQ dielectric interlayer Jul. 4, 2000
6080652 Method of fabricating a semiconductor device having a multi-layered wiring Jun. 27, 2000
6080653 Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component Jun. 27, 2000
6077764 Process for depositing high deposition rate halogen-doped silicon oxide layer Jun. 20, 2000
6071807 Fabrication method of semiconductor device including insulation film with decomposed organic content Jun. 6, 2000
6066550 Method of improving selectivity between silicon nitride and silicon oxide May. 23, 2000
6066573 Method of producing dielectric film May. 23, 2000
6060384 Borderless vias with HSQ gap filled patterned metal layers May. 9, 2000
6060383 Method for making multilayered coaxial interconnect structure May. 9, 2000
6057226 Air gap based low dielectric constant interconnect structure and method of making same May. 2, 2000
6054379 Method of depositing a low k dielectric with organo silane Apr. 25, 2000
6051448 Method of manufacturing an electronic component Apr. 18, 2000
6051491 Multilevel interconnection structure for integrated circuits and method of producing same Apr. 18, 2000
6048786 Process for forming fluorinated resin or amorphous carbon layer and devices containing same Apr. 11, 2000
6043146 Process for forming a semiconductor device Mar. 28, 2000

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