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Class Information
Number: 438/623
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Including organic insulating material between metal levels
Description: Processes wherein the intervening dielectric is at least partly composed of organic insulating material.










Patents under this class:
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Patent Number Title Of Patent Date Issued
6271116 Method of fabricating interconnects Aug. 7, 2001
6268277 Method of producing air gap for reducing intralayer capacitance in metal layers in damascene metalization process and product resulting therefrom Jul. 31, 2001
6268279 Trench and via formation in insulating films utilizing a patterned etching stopper film Jul. 31, 2001
6265303 Integrated circuit dielectric and method Jul. 24, 2001
6265779 Method and material for integration of fuorine-containing low-k dielectrics Jul. 24, 2001
6255232 Method for forming low dielectric constant spin-on-polymer (SOP) dielectric layer Jul. 3, 2001
6251470 Methods of forming insulating materials, and methods of forming insulating materials around a conductive component Jun. 26, 2001
6251802 Methods of forming carbon-containing layers Jun. 26, 2001
6245666 Method for forming a delamination resistant multi-layer dielectric layer for passivating a conductor layer Jun. 12, 2001
6245665 Semiconductor device and method of fabricating the same Jun. 12, 2001
6245659 Semiconductor device and method for manufacturing the same Jun. 12, 2001
6245658 Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system Jun. 12, 2001
6242339 Interconnect structure and method for forming the same Jun. 5, 2001
6239016 Multilevel interconnection in a semiconductor device and method for forming the same May. 29, 2001
6235628 Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer May. 22, 2001
6232238 Method for preventing corrosion of bonding pad on a surface of a semiconductor wafer May. 15, 2001
6232235 Method of forming a semiconductor device May. 15, 2001
6228780 Non-shrinkable passivation scheme for metal em improvement May. 8, 2001
6228707 Semiconductor arrangement having capacitive structure and manufacture thereof May. 8, 2001
6225217 Method of manufacturing semiconductor device having multilayer wiring May. 1, 2001
6225208 Method and structure for improved alignment tolerance in multiple, singularized plugs May. 1, 2001
6221755 Film formation method and manufacturing method of semiconductor device Apr. 24, 2001
6221779 Self-aligned process for making contacts to silicon substrates during the manufacture of integrated circuits therein Apr. 24, 2001
6218318 Semiconductor device having a porous insulation film Apr. 17, 2001
6214719 Method of implementing air-gap technology for low capacitance ILD in the damascene scheme Apr. 10, 2001
6214749 Process for producing semiconductor devices Apr. 10, 2001
6211062 Method for manufacturing semiconductor device having multiple wiring layer Apr. 3, 2001
6211093 Laser ablative removal of photoresist Apr. 3, 2001
6207556 Method of fabricating metal interconnect Mar. 27, 2001
6200912 Semiconductor device and method of producing the same Mar. 13, 2001
6197677 Method of depositing a silicon oxide layer on a semiconductor wafer Mar. 6, 2001
6187668 Method of forming self-aligned unlanded via holes Feb. 13, 2001
6188125 Via formation in polymeric materials Feb. 13, 2001
6187661 Method for fabricating metal interconnect structure Feb. 13, 2001
6187672 Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing Feb. 13, 2001
6184159 Interlayer dielectric planarization process Feb. 6, 2001
6184126 Fabricating method of dual damascene Feb. 6, 2001
6180518 Method for forming vias in a low dielectric constant material Jan. 30, 2001
6171945 CVD nanoporous silica low dielectric constant films Jan. 9, 2001
6171946 Pattern formation method for multi-layered electronic components Jan. 9, 2001
6169040 Method of manufacturing semiconductor device Jan. 2, 2001
6169023 Method for making semiconductor device Jan. 2, 2001
6165890 Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections Dec. 26, 2000
6165892 Method of planarizing thin film layers deposited over a common circuit base Dec. 26, 2000
6165893 Insulating layers and a forming method thereof Dec. 26, 2000
6165899 Method for manufacturing semiconductor devices having dual damascene structure Dec. 26, 2000
6163055 Semiconductor device and manufacturing method thereof Dec. 19, 2000
6163075 Multilayer wiring structure and semiconductor device having the same, and manufacturing method therefor Dec. 19, 2000
6159842 Method for fabricating a hybrid low-dielectric-constant intermetal dielectric (IMD) layer with improved reliability for multilevel interconnections Dec. 12, 2000
6156374 Method of forming insulating material between components of an integrated circuit Dec. 5, 2000

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