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Class Information
Number: 438/623
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) > Including organic insulating material between metal levels
Description: Processes wherein the intervening dielectric is at least partly composed of organic insulating material.

Patents under this class:
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Patent Number Title Of Patent Date Issued
6383919 Method of making a dual damascene structure without middle stop layer May. 7, 2002
6383911 Semiconductor device and method for making the same May. 7, 2002
6380076 Dielectric filling of electrical wiring planes Apr. 30, 2002
6376365 Method for fabricating semiconductor devices Apr. 23, 2002
6376359 Method of manufacturing metallic interconnect Apr. 23, 2002
6372635 Method for making a slot via filled dual damascene low k interconnect structure without middle stop layer Apr. 16, 2002
6368906 Method of planarization using selecting curing of SOG layer Apr. 9, 2002
6365503 Method of improving electromigration in semiconductor device manufacturing processes Apr. 2, 2002
6362083 Method for fabricating locally reinforced metallic microfeature Mar. 26, 2002
6358838 Semiconductor device and process for producing the same Mar. 19, 2002
6358839 Solution to black diamond film delamination problem Mar. 19, 2002
6355551 Integrated circuit having a void between adjacent conductive lines Mar. 12, 2002
6355299 Methods of transforming a material to form an insulating material between components of an integrated circuit Mar. 12, 2002
6352945 Silicone polymer insulation film on semiconductor substrate and method for forming the film Mar. 5, 2002
6352918 Method of forming inter-metal interconnection Mar. 5, 2002
6351039 Integrated circuit dielectric and method Feb. 26, 2002
6350704 Porous silicon oxycarbide integrated circuit insulator Feb. 26, 2002
6350679 Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry Feb. 26, 2002
6350672 Interconnect structure with gas dielectric compatible with unlanded vias Feb. 26, 2002
6348415 Planarization method for semiconductor device Feb. 19, 2002
6348407 Method to improve adhesion of organic dielectrics in dual damascene interconnects Feb. 19, 2002
6346470 Method for reducing electromigration in semiconductor interconnect lines Feb. 12, 2002
6346484 Method for selective extraction of sacrificial place-holding material used in fabrication of air gap-containing interconnect structures Feb. 12, 2002
6344371 Dimensionally stable core for use in high density chip packages and a method of fabricating same Feb. 5, 2002
6342454 Electronic devices with dielectric compositions and method for their manufacture Jan. 29, 2002
6337269 Method of fabricating a dual damascene structure Jan. 8, 2002
6333255 Method for making semiconductor device containing low carbon film for interconnect structures Dec. 25, 2001
6333278 Semiconductor device and manufacturing method thereof Dec. 25, 2001
6333256 Semiconductor processing method of forming openings in a material Dec. 25, 2001
6329280 Interim oxidation of silsesquioxane dielectric for dual damascene process Dec. 11, 2001
6319815 Electric wiring forming method with use of embedding material Nov. 20, 2001
6313029 Method for forming multi-layer interconnection of a semiconductor device Nov. 6, 2001
6313024 Method for forming a semiconductor device Nov. 6, 2001
6309962 Film stack and etching sequence for dual damascene Oct. 30, 2001
6306754 Method for forming wiring with extremely low parasitic capacitance Oct. 23, 2001
6303488 Semiconductor processing methods of forming openings to devices and substrates, exposing material from which photoresist cannot be substantially selectively removed Oct. 16, 2001
6300237 Semiconductor integrated circuit device and method for making the same Oct. 9, 2001
6294457 Optimized IMD scheme for using organic low-k material as IMD layer Sep. 25, 2001
6294456 Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule Sep. 25, 2001
6291333 Method of fabricating dual damascene structure Sep. 18, 2001
6288438 Semiconductor device including insulation film and fabrication method thereof Sep. 11, 2001
6287955 Integrated circuits with multiple low dielectric-constant inter-metal dielectrics Sep. 11, 2001
6284656 Copper metallurgy in integrated circuits Sep. 4, 2001
6284644 IMD scheme by post-plasma treatment of FSG and TEOS oxide capping layer Sep. 4, 2001
6281111 Semiconductor apparatus and method for fabricating the same Aug. 28, 2001
6281115 Sidewall protection for a via hole formed in a photosensitive, low dielectric constant layer Aug. 28, 2001
6277766 Method of making fullerene-decorated nanoparticles and their use as a low dielectric constant material for semiconductor devices Aug. 21, 2001
6278174 Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide Aug. 21, 2001
6277732 Method of planarizing inter-metal dielectric layer Aug. 21, 2001
6274515 Spin-on dielectric formation process for use in manufacturing semiconductors Aug. 14, 2001

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