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Class Information
Number: 438/622
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)
Description: Processes wherein there are plural levels of metal forming electrical contact material, the levels being separated by intervening dielectric material except at designated openings therethrough.

Sub-classes under this class:

Class Number Class Name Patents
438/625 At least one metallization level formed of diverse conductive layers 510
438/631 Having planarization step 759
438/623 Including organic insulating material between metal levels 951
438/636 Including use of antireflective layer 456
438/635 Insulator formed by reaction with conductor (e.g., oxidation, etc.) 222
438/641 Selective deposition 223
438/624 Separating insulating layer is laminate or composite of plural insulating materials 1,572
438/637 With formation of opening (i.e., viahole) in insulative layer 3,347

Patents under this class:

Patent Number Title Of Patent Date Issued
7226854 Methods of forming metal lines in semiconductor devices Jun. 5, 2007
7226853 Method of forming a dual damascene structure utilizing a three layer hard mask structure Jun. 5, 2007
7223690 Substrate processing method May. 29, 2007
7223687 Printed wiring board and method of fabricating the same May. 29, 2007
7223686 Semiconductor interconnection line and method of forming the same May. 29, 2007
7223685 Damascene fabrication with electrochemical layer removal May. 29, 2007
7223680 Method of forming a dual damascene metal trace with reduced RF impedance resulting from the skin effect May. 29, 2007
7220665 H.sub.2 plasma treatment May. 22, 2007
7217651 Interconnects with interlocks May. 15, 2007
7217650 Metallic nanowire interconnections for integrated circuit fabrication May. 15, 2007
7217649 System and method for stress free conductor removal May. 15, 2007
7214608 Interlevel dielectric layer and metal layer sealing May. 8, 2007
7211512 Selective electroless-plated copper metallization May. 1, 2007
7211506 Methods of forming cobalt layers for semiconductor devices May. 1, 2007
7208402 Method and apparatus for improved power routing Apr. 24, 2007
7208341 Method for manufacturing printed circuit board Apr. 24, 2007
7205241 Method for manufacturing semiconductor device with contact body extended in direction of bit line Apr. 17, 2007
7205230 Process for manufacturing a wiring board having a via Apr. 17, 2007
7205227 Methods of forming CMOS constructions Apr. 17, 2007
7205224 Very low dielectric constant plasma-enhanced CVD films Apr. 17, 2007
7205223 Method of forming an interconnect structure for a semiconductor device Apr. 17, 2007
7205209 Fabrication of stacked dielectric layer for suppressing electrostatic charge buildup Apr. 17, 2007
7205180 Process of fabricating semiconductor packages using leadframes roughened with chemical etchant Apr. 17, 2007
7202158 Method for fabricating a metal-insulator-metal capacitor Apr. 10, 2007
7202157 Method for forming metallic interconnects in semiconductor devices Apr. 10, 2007
7202156 Process for manufacturing a wiring substrate Apr. 10, 2007
7202155 Method for manufacturing wiring and method for manufacturing semiconductor device Apr. 10, 2007
7202154 Suspension for filling via holes in silicon and method for making the same Apr. 10, 2007
7202153 Method for forming, under a thin layer of a first material, portions of another material and/or empty areas Apr. 10, 2007
7199471 Method and apparatus for reducing capacitive coupling between lines in an integrated circuit Apr. 3, 2007
7199040 Barrier layer structure Apr. 3, 2007
7198991 Method of manufacturing an active matrix display device Apr. 3, 2007
7196003 Method for manufacturing a semiconductor device suitable for the formation of a wiring layer Mar. 27, 2007
7192871 Semiconductor device with a line and method of fabrication thereof Mar. 20, 2007
7190078 Interlocking via for package via integrity Mar. 13, 2007
7189657 Semiconductor substrate surface protection method Mar. 13, 2007
7189597 Semiconductor device and method for fabricating the same Mar. 13, 2007
7189596 Process for forming a direct build-up layer on an encapsulated die packages utilizing intermediate structures Mar. 13, 2007
7186641 Methods of forming metal interconnection lines in semiconductor devices Mar. 6, 2007
7186640 Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics Mar. 6, 2007
7186638 Passivation processes for use with metallization techniques Mar. 6, 2007
7183198 Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes Feb. 27, 2007
7183197 Water-barrier performance of an encapsulating film Feb. 27, 2007
7183196 Multilayer interconnection board and production method thereof Feb. 27, 2007
7183195 Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler Feb. 27, 2007
7180195 Method and apparatus for improved power routing Feb. 20, 2007
7179733 Method of forming contact holes and electronic device formed thereby Feb. 20, 2007
7179732 Interconnection structure and fabrication method thereof Feb. 20, 2007
7176133 Controlled electroless plating Feb. 13, 2007
7176120 Method of manufacturing semiconductor device Feb. 13, 2007

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