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Class Information
Number: 438/622
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects) > Multiple metal levels, separated by insulating layer (i.e., multiple level metallization)
Description: Processes wherein there are plural levels of metal forming electrical contact material, the levels being separated by intervening dielectric material except at designated openings therethrough.

Sub-classes under this class:

Class Number Class Name Patents
438/625 At least one metallization level formed of diverse conductive layers 510
438/631 Having planarization step 759
438/623 Including organic insulating material between metal levels 951
438/636 Including use of antireflective layer 456
438/635 Insulator formed by reaction with conductor (e.g., oxidation, etc.) 222
438/641 Selective deposition 223
438/624 Separating insulating layer is laminate or composite of plural insulating materials 1,572
438/637 With formation of opening (i.e., viahole) in insulative layer 3,347

Patents under this class:

Patent Number Title Of Patent Date Issued
8709947 Method for forming pattern Apr. 29, 2014
8709943 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region Apr. 29, 2014
8709940 Structure of circuit board and method for fabricating the same Apr. 29, 2014
8709939 Semiconductor device having a multilevel interconnect structure and method for fabricating the same Apr. 29, 2014
8709937 Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same Apr. 29, 2014
8704374 Semiconductor device and method for manufacturing the same Apr. 22, 2014
8691690 Contact formation method incorporating preventative etch step reducing interlayer dielectric material flake defects Apr. 8, 2014
8691689 Methods for fabricating integrated circuits having low resistance device contacts Apr. 8, 2014
8691633 Metal structure for memory device Apr. 8, 2014
8679967 Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning Mar. 25, 2014
8679965 Semiconductor device having a reduced bit line parasitic capacitance and method for manufacturing the same Mar. 25, 2014
8679894 Low temperature deposition of phase change memory materials Mar. 25, 2014
8674508 Seal ring structures with reduced moisture-induced reliability degradation Mar. 18, 2014
8674484 Dielectric separator layer Mar. 18, 2014
8673775 Methods of forming semiconductor structures Mar. 18, 2014
8673770 Methods of forming conductive structures in dielectric layers on an integrated circuit device Mar. 18, 2014
8673765 Method and apparatus for back end of line semiconductor device processing Mar. 18, 2014
8669661 Metal line and via formation using hard masks Mar. 11, 2014
8669597 Memory device interconnects and method of manufacturing Mar. 11, 2014
8669176 BEOL integration scheme for copper CMP to prevent dendrite formation Mar. 11, 2014
8664763 Semiconductor apparatus, electronic device, and method of manufacturing semiconductor apparatus Mar. 4, 2014
8664759 Integrated circuit with heat conducting structures for localized thermal control Mar. 4, 2014
8664113 Multilayer interconnect structure and method for integrated circuits Mar. 4, 2014
8664108 Stacked multilayer structure and manufacturing method thereof Mar. 4, 2014
8664044 Method of fabricating land grid array semiconductor package Mar. 4, 2014
8658529 Method for manufacturing semiconductor device Feb. 25, 2014
8652962 Etch damage and ESL free dual damascene metal interconnect Feb. 18, 2014
8652960 Active area bonding compatible high current structures Feb. 18, 2014
8648467 Semiconductor memory device and method of manufacturing the same Feb. 11, 2014
8648444 Wafer scribe line structure for improving IC reliability Feb. 11, 2014
8647977 Methods of forming interconnects Feb. 11, 2014
8643178 Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same Feb. 4, 2014
8637982 Split loop cut pattern for spacer process Jan. 28, 2014
8637400 Interconnect structures and methods for back end of the line integration Jan. 28, 2014
8633591 Electronic device Jan. 21, 2014
8633099 Method for forming interlayer connectors in a three-dimensional stacked IC device Jan. 21, 2014
8629556 Semiconductor device Jan. 14, 2014
8629048 Methods of forming a pattern on a substrate Jan. 14, 2014
8624396 Apparatus and method for low contact resistance carbon nanotube interconnect Jan. 7, 2014
8624381 Integrated antennas in wafer level package Jan. 7, 2014
8623699 Method of chip package build-up Jan. 7, 2014
8617982 Subtractive patterning to define circuit components Dec. 31, 2013
8617981 Semiconductor device and manufacturing method thereof Dec. 31, 2013
8617980 Semiconductor device including capacitor Dec. 31, 2013
8617979 Method for manufacturing semiconductor device and semiconductor device Dec. 31, 2013
8614515 Wiring method for semiconductor integrated circuit, semiconductor-circuit wiring apparatus and semiconductor integrated circuit Dec. 24, 2013
8614143 Simultaneous via and trench patterning using different etch rates Dec. 24, 2013
8609532 Magnetically sintered conductive via Dec. 17, 2013
8609530 Method for forming a three-dimensional structure of metal-insulator-metal type Dec. 17, 2013
8609529 Fabrication method and structure of through silicon via Dec. 17, 2013

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