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Class Information
Number: 438/618
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects)
Description: Processes wherein the electrical contact is formed so as to make electrical contact to plural semiconductive regions










Sub-classes under this class:

Class Number Class Name Patents
438/619 Air bridge structure 512
438/621 Contacting diversely doped semiconductive regions (e.g., p-type and n-type regions, etc.) 190
438/642 Diverse conductors 261
438/620 Forming contacts of differing depths into semiconductor substrate 405
438/622 Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) 2,472


Patents under this class:
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Patent Number Title Of Patent Date Issued
7160795 Method and structures for reduced parasitic capacitance in integrated circuit metallizations Jan. 9, 2007
7157372 Coaxial through chip connection Jan. 2, 2007
7157369 Semiconductor device and method of manufacturing thereof Jan. 2, 2007
7157366 Method of forming metal interconnection layer of semiconductor device Jan. 2, 2007
7154183 Semiconductor device having multilevel interconnection Dec. 26, 2006
7153766 Metal barrier cap fabrication by polymer lift-off Dec. 26, 2006
7151052 Multiple etch-stop layer deposition scheme and materials Dec. 19, 2006
7148144 Method of forming copper sulfide layer over substrate Dec. 12, 2006
7148143 Semiconductor device having a fully silicided gate electrode and method of manufacture therefor Dec. 12, 2006
7148136 Method of producing ceramic multi-layer substrate Dec. 12, 2006
7146597 CAD method for arranging via-holes, a CAD tool, photomasks produced by the CAD method, a semiconductor integrated circuit manufactured with photomasks and a computer program product for execut Dec. 5, 2006
7144802 Vapor deposition of benzotriazole (BTA) for protecting copper interconnects Dec. 5, 2006
7141493 Semiconductor device, method of manufacturing three-dimensional stacking type semiconductor device, circuit board, and electronic instrument Nov. 28, 2006
7138295 Method of information processing using three dimensional integrated circuits Nov. 21, 2006
7135408 Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure Nov. 14, 2006
7135398 Reliable low-k interconnect structure with hybrid dielectric Nov. 14, 2006
7135354 Semiconductor device and method of manufacturing the same, semiconductor wafer, circuit board and electronic instrument Nov. 14, 2006
7132361 System for and method of forming via holes by multiple deposition events in a continuous inline shadow mask deposition process Nov. 7, 2006
7129159 Integrated dual damascene RIE process with organic patterning layer Oct. 31, 2006
7125792 Dual damascene structure and method Oct. 24, 2006
7122899 Semiconductor device and production process Oct. 17, 2006
7122461 Method to assemble structures from nano-materials Oct. 17, 2006
7122458 Method for fabricating pad redistribution layer Oct. 17, 2006
7122456 Method for reduced input output area Oct. 17, 2006
7119009 Semiconductor device with dual damascene wiring Oct. 10, 2006
7119005 Semiconductor local interconnect and contact Oct. 10, 2006
7119001 Semiconductor chip packages and methods for fabricating the same Oct. 10, 2006
7118925 Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step Oct. 10, 2006
7112525 Method for the assembly of nanowire interconnects Sep. 26, 2006
7109070 Production of a composite material having a biodegradable plastic substrate and at least one coating Sep. 19, 2006
7105451 Method for manufacturing semiconductor device Sep. 12, 2006
7105463 Load lock chamber having two dual slot regions Sep. 12, 2006
7101773 Method of producing a contact system on the rear of a component with stacked substrates Sep. 5, 2006
7101783 Method for forming bit-line of semiconductor device Sep. 5, 2006
7102233 Structure for strained channel field effect transistor pair having underlapped dual liners Sep. 5, 2006
7098124 Method of forming contact hole and method of fabricating semiconductor device Aug. 29, 2006
7098536 Structure for strained channel field effect transistor pair having a member and a contact via Aug. 29, 2006
7093356 Method for producing wiring substrate Aug. 22, 2006
7094674 Method for production of contacts on a wafer Aug. 22, 2006
7094679 Carbon nanotube interconnect Aug. 22, 2006
7094680 Formation of a tantalum-nitride layer Aug. 22, 2006
7091081 Method for patterning a semiconductor region Aug. 15, 2006
7087515 Method for forming flowable dielectric layer in semiconductor device Aug. 8, 2006
7084058 Method of forming low-loss coplanar waveguides Aug. 1, 2006
7078331 Method of forming redistribution bump and semiconductor chip and mount structure fabricated using the same Jul. 18, 2006
7074706 Semiconductor device and wiring forming method in semiconductor device Jul. 11, 2006
7074722 Method for fabricating semiconductor device with fine pattern Jul. 11, 2006
7064055 Method of forming a multi-layer semiconductor structure having a seamless bonding interface Jun. 20, 2006
7064059 Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer Jun. 20, 2006
7060603 Methods of forming metal wiring of semiconductor devices including sintering the wiring layers and forming a via hole with a barrier metal Jun. 13, 2006

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