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Class Information
Number: 438/618
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Contacting multiple semiconductive regions (i.e., interconnects)
Description: Processes wherein the electrical contact is formed so as to make electrical contact to plural semiconductive regions










Sub-classes under this class:

Class Number Class Name Patents
438/619 Air bridge structure 512
438/621 Contacting diversely doped semiconductive regions (e.g., p-type and n-type regions, etc.) 190
438/642 Diverse conductors 261
438/620 Forming contacts of differing depths into semiconductor substrate 405
438/622 Multiple metal levels, separated by insulating layer (i.e., multiple level metallization) 2,472


Patents under this class:

Patent Number Title Of Patent Date Issued
8710671 Multi-level integrated circuit, device and method for modeling multi-level integrated circuits Apr. 29, 2014
8710667 Semiconductor device Apr. 29, 2014
8709939 Semiconductor device having a multilevel interconnect structure and method for fabricating the same Apr. 29, 2014
8709938 3D IC method and device Apr. 29, 2014
8709937 Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same Apr. 29, 2014
8704353 Thermal management of stacked semiconductor chips with electrically non-functional interconnects Apr. 22, 2014
8704342 Resin sealing type semiconductor device and method of manufacturing the same, and lead frame Apr. 22, 2014
8703507 Method and apparatus to improve reliability of vias Apr. 22, 2014
8692364 Semiconductor device and method for manufacturing the same Apr. 8, 2014
8691690 Contact formation method incorporating preventative etch step reducing interlayer dielectric material flake defects Apr. 8, 2014
8691656 Methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM Apr. 8, 2014
8685809 Semiconductor structures having improved contact resistance Apr. 1, 2014
8681596 Seek-scan probe (SSP) memory with sharp probe tips formed at CMOS-compatible temperatures Mar. 25, 2014
8680682 Barrier for through-silicon via Mar. 25, 2014
8679932 System and method for manufacturing thin film resistors using a trench and chemical mechanical polishing Mar. 25, 2014
8679911 Cross-coupling-based design using diffusion contact structures Mar. 25, 2014
8673763 Stacked digital/RF system-on-chip with integral isolation layer Mar. 18, 2014
8669180 Semiconductor device with self aligned end-to-end conductive line structure and method of forming the same Mar. 11, 2014
8669175 Semiconductor device and manufacturing of the semiconductor device Mar. 11, 2014
8664766 Interconnect structure containing non-damaged dielectric and a via gouging feature Mar. 4, 2014
8664113 Multilayer interconnect structure and method for integrated circuits Mar. 4, 2014
8659115 Airgap-containing interconnect structure with improved patternable low-K material and method of fabricating Feb. 25, 2014
8658531 Method of forming connection holes Feb. 25, 2014
8653665 Barrier layer, film forming method, and processing system Feb. 18, 2014
8652960 Active area bonding compatible high current structures Feb. 18, 2014
8647982 Methods of forming interconnects in a semiconductor structure Feb. 11, 2014
8647978 Use of graphene to limit copper surface oxidation, diffusion and electromigration in interconnect structures Feb. 11, 2014
8647976 Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same Feb. 11, 2014
8644063 Fabrication and integration of devices with top and bottom electrodes including magnetic tunnel junctions Feb. 4, 2014
8642464 Method of manufacturing semiconductor device Feb. 4, 2014
8637997 Semiconductor device and method of manufacturing the same Jan. 28, 2014
8637400 Interconnect structures and methods for back end of the line integration Jan. 28, 2014
8637395 Methods for photo-patternable low-k (PPLK) integration with curing after pattern transfer Jan. 28, 2014
8633601 Interconnect assemblies and methods of making and using same Jan. 21, 2014
8633104 Methods of manufacturing three-dimensional semiconductor devices Jan. 21, 2014
8629548 Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node Jan. 14, 2014
8629060 Methods of forming through substrate interconnects Jan. 14, 2014
8618674 Semiconductor device including a sintered insulation material Dec. 31, 2013
8618568 Method for manufacturing light-emitting device and film formation substrate Dec. 31, 2013
8617970 Method of manufacturing semiconductor device Dec. 31, 2013
8614509 Semiconductor device having a multi-layered line and manufacturing method of the same Dec. 24, 2013
8614143 Simultaneous via and trench patterning using different etch rates Dec. 24, 2013
8610278 Use of graphene to limit copper surface oxidation, diffusion and electromigration in interconnect structures Dec. 17, 2013
8610267 Reducing delamination between an underfill and a buffer layer in a bond structure Dec. 17, 2013
8609529 Fabrication method and structure of through silicon via Dec. 17, 2013
8609528 High-density patterning Dec. 17, 2013
8598710 Semiconductor device with dummy contacts Dec. 3, 2013
8598032 Reduced number of masks for IC device with stacked contact levels Dec. 3, 2013
8598031 Reliable interconnect for semiconductor device Dec. 3, 2013
8592987 Semiconductor element comprising a supporting structure and production method Nov. 26, 2013











 
 
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