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Class Information
Number: 438/599
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > To form ohmic contact to semiconductive material > Selectively interconnecting (e.g., customization, wafer scale integration, etc.) > With electrical circuit layout
Description: Processes including a step of designing the topological arrangement of electrical conductors between arrayed device components.










Patents under this class:
1 2 3 4 5 6

Patent Number Title Of Patent Date Issued
5972740 Layout algorithm for generating power supply interconnections for an LSI circuit Oct. 26, 1999
5966628 Process design for wafer edge in vlsi Oct. 12, 1999
5956618 Process for producing multi-level metallization in an integrated circuit Sep. 21, 1999
5913101 Semiconductor device manufacturing method by carrying out logic design Jun. 15, 1999
5899706 Method of reducing loading variation during etch processing May. 4, 1999
5885857 Semiconductor chip capable of suppressing cracks in the insulating layer Mar. 23, 1999
5872027 Master slice type integrated circuit system having block areas optimized based on function Feb. 16, 1999
5869357 Metallization and wire bonding process for manufacturing power semiconductor devices Feb. 9, 1999
5858817 Process to personalize master slice wafers and fabricate high density VLSI components with a single masking step Jan. 12, 1999
5840619 Method of making a semiconductor device having a planarized surface Nov. 24, 1998
5837557 Semiconductor fabrication method of forming a master layer to combine individually printed blocks of a circuit pattern Nov. 17, 1998
5817577 Grounding method for eliminating process antenna effect Oct. 6, 1998
5801091 Method for current ballasting and busing over active device area using a multi-level conductor process Sep. 1, 1998
5798285 Method of making electronic module with multiple solder dams in soldermask window Aug. 25, 1998
5789313 Process for producing a semiconductor device with a planar top surface Aug. 4, 1998
5783480 Layout method for semiconductor memory device obtaining high bandwidth and signal line Jul. 21, 1998
5747380 Robust end-point detection for contact and via etching May. 5, 1998
5741730 Flexible IC layout method Apr. 21, 1998
5733798 Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization Mar. 31, 1998
5721151 Method of fabricating a gate array integrated circuit including interconnectable macro-arrays Feb. 24, 1998
5705407 Method of forming high performance bipolar devices with improved wiring options Jan. 6, 1998
5671397 Sea-of-cells array of transistors Sep. 23, 1997
5652163 Use of reticle stitching to provide design flexibility Jul. 29, 1997
5650348 Method of making an integrated circuit chip having an array of logic gates Jul. 22, 1997
5620916 Method for improving via/contact coverage in an integrated circuit Apr. 15, 1997
5618744 Manufacturing method and apparatus of a semiconductor integrated circuit device Apr. 8, 1997
5610831 Semiconductor element layout method employing process migration Mar. 11, 1997
5610093 Method of manufacturing a programmable hybrid balance network Mar. 11, 1997
5565386 Method of connecting to integrated circuitry Oct. 15, 1996
5556805 Method for producing semiconductor device having via hole Sep. 17, 1996
5547887 Method of making a CMOS output pad driver with variable drive currents, ESD protection and improved leakage current behavior Aug. 20, 1996
5548747 Bit stack wiring channel optimization with fixed macro placement and variable pin placement Aug. 20, 1996
5508938 Special interconnect layer employing offset trace layout for advanced multi-chip module packages Apr. 16, 1996
5506162 Method of producing a semiconductor integrated circuit device using a master slice approach Apr. 9, 1996
5498767 Method for positioning bond pads in a semiconductor die layout Mar. 12, 1996
5498579 Method of producing semiconductor device layer layout Mar. 12, 1996
5494853 Method to solve holes in passivation by metal layout Feb. 27, 1996
5494842 Method of programming a CMOS read only memory at the second metal layer in a two-metal process Feb. 27, 1996
5459093 Method for forming dummy pattern in a semiconductor device Oct. 17, 1995
5424248 Method of making an integrated circuit with variable pad pitch Jun. 13, 1995
5393701 Layout design to eliminate process antenna effect Feb. 28, 1995
5394337 Method for wire routing of a semiconductor integrated circuit and apparatus for implementing the same Feb. 28, 1995
5391900 Integrated circuit having power trunk line and method for layout of power trunk line Feb. 21, 1995
5360767 Method for assigning pins to connection points Nov. 1, 1994
5348902 Method of designing cells applicable to different design automation systems Sep. 20, 1994
5322438 Layout scheme for precise capacitance ratios Jun. 21, 1994
5300815 Technique of increasing bond pad density on a semiconductor die Apr. 5, 1994
5292687 Process for lay-out of a semiconductor integrated circuit Mar. 8, 1994
5278105 Semiconductor device with dummy features in active layers Jan. 11, 1994
5264390 Method of automatic wiring in a semiconductor device Nov. 23, 1993

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