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Class Information
Number: 438/595
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > Insulated gate formation > Having sidewall structure
Description: Processes wherein the insulated gate electrode has material features formed along the electrode sidewall.


Sub-classes under this class:

Class Number Class Name Patents
438/596 Portion of sidewall structure is conductive 285


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Patent Number Title Of Patent Date Issued
7622337 Method for fabricating a transistor using a SOI wafer Nov. 24, 2009
7618862 Flash memory device and method for manufacturing the same Nov. 17, 2009
7618868 Method of manufacturing field effect transistors using sacrificial blocking layers Nov. 17, 2009
7608512 Integrated circuit structure with improved LDMOS design Oct. 27, 2009
7601574 Methods for fabricating a stress enhanced MOS transistor Oct. 13, 2009
7598140 Method of producing a semiconductor device having an oxide film Oct. 6, 2009
7592215 Semiconductor device having self-aligned contact hole and method of fabricating the same Sep. 22, 2009
7592231 MOS transistor and fabrication thereof Sep. 22, 2009
7589006 Method for manufacturing semiconductor device Sep. 15, 2009
7585734 Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby Sep. 8, 2009
7585773 Non-conformal stress liner for enhanced MOSFET performance Sep. 8, 2009
7585786 Methods of forming spin-on-glass insulating layers in semiconductor devices and associated semiconductor device Sep. 8, 2009
7582567 Method for forming CMOS device with self-aligned contacts and region formed using salicide process Sep. 1, 2009
7579228 Disposable organic spacers Aug. 25, 2009
7575997 Method for forming contact hole of semiconductor device Aug. 18, 2009
7572719 Semiconductor device and manufacturing method thereof Aug. 11, 2009
7572692 Complementary transistors having different source and drain extension spacing controlled by different spacer sizes Aug. 11, 2009
7572702 Split gate type non-volatile memory device Aug. 11, 2009
7560329 Semiconductor device and method for fabricating the same Jul. 14, 2009
7557024 Single poly CMOS imager Jul. 7, 2009
7544594 Method of forming a transistor having gate protection and transistor formed according to the method Jun. 9, 2009
7544595 Forming a semiconductor device having a metal electrode and structure thereof Jun. 9, 2009
7538018 Gate structure and method for fabricating the same, and method for fabricating memory and CMOS transistor layout May. 26, 2009
7534711 System and method for direct etching May. 19, 2009
7521314 Method for selective removal of a layer Apr. 21, 2009
7517806 Integrated circuit having pairs of parallel complementary FinFETs Apr. 14, 2009
7517781 Method of manufacturing semiconductor device Apr. 14, 2009
7518179 Virtual ground memory array and method therefor Apr. 14, 2009
7514367 Method for manufacturing a narrow structure on an integrated circuit Apr. 7, 2009
7501317 Method of manufacturing semiconductor device Mar. 10, 2009
7498264 Method to obtain fully silicided poly gate Mar. 3, 2009
7485579 Method of manufacturing a semiconductor device Feb. 3, 2009
7482231 Manufacturing of memory array and periphery Jan. 27, 2009
7482236 Structure and method for a sidewall SONOS memory device Jan. 27, 2009
7482623 Organic semiconductor film and organic semiconductor device Jan. 27, 2009
7479436 Feed forward silicide control scheme based on spacer height controlling preclean time Jan. 20, 2009
7470606 Masking methods Dec. 30, 2008
7462554 Method for forming semiconductor device with modified channel compressive stress Dec. 9, 2008
7459384 Preventing cavitation in high aspect ratio dielectric regions of semiconductor device Dec. 2, 2008
7456066 Variable width offset spacers for mixed signal and system on chip devices Nov. 25, 2008
7449403 Method for manufacturing semiconductor device Nov. 11, 2008
7446354 Power semiconductor device having improved performance and method Nov. 4, 2008
7446027 Method for forming gate structure with local pulled-back conductive layer and its use Nov. 4, 2008
7446006 Semiconductor fabrication process including silicide stringer removal processing Nov. 4, 2008
7446007 Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof Nov. 4, 2008
7446004 Method for reducing overlap capacitance in field effect transistors Nov. 4, 2008
7439138 Method of forming integrated circuitry Oct. 21, 2008
7425498 Semiconductor device with dummy electrode Sep. 16, 2008
7422971 Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby Sep. 9, 2008
7419876 Method for manufacturing non-volatile memory devices integrated in a semiconductor substrate Sep. 2, 2008

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