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Class Information
Number: 438/587
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > Insulated gate formation > Forming array of gate electrodes
Description: Process involving the deposition of electrically conductive material resulting in the formation of a repeating geometrical arrangement (e.g., multiple, adjacent electrically conductive elements) of coplanar gate electrodes.

Sub-classes under this class:

Class Number Class Name Patents
438/588 Plural gate levels 321

Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13

Patent Number Title Of Patent Date Issued
6794280 Method of fabricating non-volatile memory Sep. 21, 2004
6790732 Self-aligned dual-gate transistor device and method of forming self-aligned dual-gate transistor device Sep. 14, 2004
6784061 Process to improve the Vss line formation for high density flash memory and related structure associated therewith Aug. 31, 2004
6777289 Processing methods of forming an electrically conductive plug to a node location Aug. 17, 2004
6770501 Deuterium reservoirs and ingress paths Aug. 3, 2004
6770521 Method of making multiple work function gates by implanting metals with metallic alloying additives Aug. 3, 2004
6767774 Producing multi-color stable light emitting organic displays Jul. 27, 2004
6767814 Semiconductor device having silicide thin film and method of forming the same Jul. 27, 2004
6767795 Highly reliable amorphous high-k gate dielectric ZrOXNY Jul. 27, 2004
6764901 Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor Jul. 20, 2004
6765245 Gate array core cell for VLSI ASIC devices Jul. 20, 2004
6762084 Integrated circuit having a memory cell transistor with a gate oxide layer which is thicker than the gate oxide layer of a peripheral circuit transistor Jul. 13, 2004
6756284 Method for forming a sublithographic opening in a semiconductor process Jun. 29, 2004
6753209 Gate array architecture Jun. 22, 2004
6746943 Semiconductor device and method of fabricating the same Jun. 8, 2004
6737338 Pattern forming method for a display device May. 18, 2004
6737294 Method of reducing surface leakage currents of a thin-film transistor substrate May. 18, 2004
6734071 Methods of forming insulative material against conductive structures May. 11, 2004
6730553 Methods for making semiconductor structures having high-speed areas and high-density areas May. 4, 2004
6723607 Method of forming fine patterns of semiconductor device Apr. 20, 2004
6716046 Field effect transistor structure with self-aligned raised source/drain extensions Apr. 6, 2004
6709937 Transistor structures Mar. 23, 2004
6706576 Laser thermal annealing of silicon nitride for increased density and etch selectivity Mar. 16, 2004
6703266 Method for fabricating thin film transistor array and driving circuit Mar. 9, 2004
6703291 Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions Mar. 9, 2004
6699755 Method for producing a gate Mar. 2, 2004
6689676 Method for forming a semiconductor device structure in a semiconductor layer Feb. 10, 2004
6686625 Field effect-controllable semiconductor component with two-directional blocking, and a method of producing the semiconductor component Feb. 3, 2004
6682997 Angled implant in a fabrication technique to improve conductivity of a base material Jan. 27, 2004
6664173 Hardmask gate patterning technique for all transistors using spacer gate approach for critical dimension control Dec. 16, 2003
6664153 Method to fabricate a single gate with dual work-functions Dec. 16, 2003
6656753 Method and structure for measuring bridge induced by mask layout amendment Dec. 2, 2003
6649501 Method for forming a bit line for a semiconductor device Nov. 18, 2003
6649500 Semiconductor device including an insulated gate field effect transistor and method of manufacturing the same Nov. 18, 2003
6649502 Methods of forming multilayer dielectric regions using varied deposition parameters Nov. 18, 2003
6638829 Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture Oct. 28, 2003
6627471 Method of manufacturing an array substrate having drive integrated circuits Sep. 30, 2003
6620717 Memory with disposable ARC for wordline formation Sep. 16, 2003
6613655 Method of fabricating system on chip device Sep. 2, 2003
6613621 Methods of forming self-aligned contact pads using a damascene gate process Sep. 2, 2003
6610574 Process for forming MOSgated device with trench structure and remote contact Aug. 26, 2003
6602773 Methods of fabricating semiconductor devices having protected plug contacts and upper interconnections Aug. 5, 2003
6593190 Non-volatile memory device having a bit line contact pad and method for manufacturing the same Jul. 15, 2003
6566194 Salicided gate for virtual ground arrays May. 20, 2003
6551876 Processing methods of forming an electrically conductive plug to a node location Apr. 22, 2003
6548394 Method of forming contact plugs Apr. 15, 2003
6548388 Semiconductor device including gate electrode having damascene structure and method of fabricating the same Apr. 15, 2003
6538269 Gate array and manufacturing method of semiconductor integrated circuit using gate array Mar. 25, 2003
6531371 Electrically programmable resistance cross point memory Mar. 11, 2003
6531359 Method for fabricating a memory cell array Mar. 11, 2003

1 2 3 4 5 6 7 8 9 10 11 12 13

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