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Class Information
Number: 438/587
Name: Semiconductor device manufacturing: process > Coating with electrically or thermally conductive material > Insulated gate formation > Forming array of gate electrodes
Description: Process involving the deposition of electrically conductive material resulting in the formation of a repeating geometrical arrangement (e.g., multiple, adjacent electrically conductive elements) of coplanar gate electrodes.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 8685850 |
System and method of plating conductive gate contacts on metal gates for self-aligned contact interconnections |
Apr. 1, 2014 |
| 8679923 |
Method for forming metal gate |
Mar. 25, 2014 |
| 8680623 |
Techniques for enabling multiple V.sub.t devices using high-K metal gate stacks |
Mar. 25, 2014 |
| 8664071 |
Castellated gate MOSFET tetrode capable of fully-depleted operation |
Mar. 4, 2014 |
| 8658502 |
Method for reducing morphological difference between N-doped and undoped polysilicon gates after etching |
Feb. 25, 2014 |
| 8658524 |
On-gate contacts in a MOS device |
Feb. 25, 2014 |
| 8658526 |
Methods for increased array feature density |
Feb. 25, 2014 |
| 8652909 |
Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells array of nonvolatile memory cells |
Feb. 18, 2014 |
| 8652904 |
Semiconductor device with gate trench |
Feb. 18, 2014 |
| 8647938 |
SRAM integrated circuits with buried saddle-shaped FINFET and methods for their fabrication |
Feb. 11, 2014 |
| 8647952 |
Encapsulation of closely spaced gate electrode structures |
Feb. 11, 2014 |
| 8642458 |
Method of fabricating nonvolatile memory device |
Feb. 4, 2014 |
| 8637362 |
Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
Jan. 28, 2014 |
| 8637389 |
Resist feature and removable spacer pitch doubling patterning method for pillar structures |
Jan. 28, 2014 |
| 8635573 |
Method of fabricating a semiconductor device having a defined minimum gate spacing between adjacent gate structures |
Jan. 21, 2014 |
| 8629048 |
Methods of forming a pattern on a substrate |
Jan. 14, 2014 |
| 8623716 |
Multi-gate semiconductor devices and methods of forming the same |
Jan. 7, 2014 |
| 8617974 |
Method of manufacturing semiconductor device and semiconductor device |
Dec. 31, 2013 |
| 8617996 |
Fin removal method |
Dec. 31, 2013 |
| 8618604 |
Semiconductor device and method of manufacturing the same |
Dec. 31, 2013 |
| 8618616 |
FinFET structures and methods for fabricating the same |
Dec. 31, 2013 |
| 8610176 |
Standard cell architecture using double poly patterning for multi VT devices |
Dec. 17, 2013 |
| 8610205 |
Inter-poly dielectric in a shielded gate MOSFET device |
Dec. 17, 2013 |
| 8598028 |
Gate height loss improvement for a transistor |
Dec. 3, 2013 |
| 8586436 |
Method of forming a variety of replacement gate types including replacement gate types on a hybrid semiconductor device |
Nov. 19, 2013 |
| 8586462 |
Method of manufacturing a field-effect transistor |
Nov. 19, 2013 |
| 8581308 |
High temperature embedded charge devices and methods thereof |
Nov. 12, 2013 |
| 8581322 |
Nonvolatile memory device and method for making the same |
Nov. 12, 2013 |
| 8575013 |
Replacement gate fabrication methods |
Nov. 5, 2013 |
| 8563410 |
End-cut first approach for critical dimension control |
Oct. 22, 2013 |
| 8546252 |
Metal gate FET having reduced threshold voltage roll-off |
Oct. 1, 2013 |
| 8541284 |
Method of manufacturing string floating gates with air gaps in between |
Sep. 24, 2013 |
| 8541826 |
Memory array structure and method for forming the same |
Sep. 24, 2013 |
| 8530942 |
Semiconductor device and method of fabricating the same |
Sep. 10, 2013 |
| 8518757 |
Method of fabricating strained semiconductor structures from silicon-on-insulator (SOI) |
Aug. 27, 2013 |
| 8518812 |
Methods of forming electrical contacts |
Aug. 27, 2013 |
| 8513105 |
Flexible integration of logic blocks with transistors of different threshold voltages |
Aug. 20, 2013 |
| 8507997 |
Mask read-only memory having a fake select transistor |
Aug. 13, 2013 |
| 8507380 |
Methods of forming contact openings and methods of increasing contact area in only one of X and Y axes in the fabrication of integrated circuitry |
Aug. 13, 2013 |
| 8501607 |
FinFET alignment structures using a double trench flow |
Aug. 6, 2013 |
| 8497198 |
Semiconductor process |
Jul. 30, 2013 |
| 8487397 |
Method for forming self-aligned contact |
Jul. 16, 2013 |
| 8486840 |
Inverse spacer processing |
Jul. 16, 2013 |
| 8486817 |
Method for forming an integrated circuit level by sequential tridimensional integration |
Jul. 16, 2013 |
| 8470647 |
Semiconductor device and manufacturing method thereof |
Jun. 25, 2013 |
| 8460996 |
Semiconductor devices with different dielectric thicknesses |
Jun. 11, 2013 |
| 8461628 |
MOS transistor with laser-patterned metal gate, and method for making the same |
Jun. 11, 2013 |
| 8455342 |
Mask ROM fabrication method |
Jun. 4, 2013 |
| 8431458 |
Methods of forming a nonvolatile memory cell and methods of forming an array of nonvolatile memory cells |
Apr. 30, 2013 |
| 8426301 |
Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices |
Apr. 23, 2013 |
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