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Class Information
Number: 438/564
Name: Semiconductor device manufacturing: process > Introduction of conductivity modifying dopant into semiconductive material > Diffusing a dopant > From solid dopant source in contact with semiconductor region > Polycrystalline semiconductor source
Description: Processes wherein the solid dopant source material is composed of a multicrystalline semiconductor (i.e., polysilicon).

Patents under this class:
1 2 3 4 5

Patent Number Title Of Patent Date Issued
5843834 Self-aligned POCL.sub.3 process flow for submicron microelectronics applications using amorphized polysilicon Dec. 1, 1998
5827760 Method for fabricating a thin film transistor of a liquid crystal display device Oct. 27, 1998
5827768 Method for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structure Oct. 27, 1998
5814541 Method for manufacturing semiconductor device Sep. 29, 1998
5804476 Method of forming BiCMOS devices having mosfet and bipolar sections therein Sep. 8, 1998
5801087 Method of forming improved contacts from polysilicon to siliconor other polysilicon layers Sep. 1, 1998
5798295 Method for forming a buried contact on a semiconductor substrate Aug. 25, 1998
5789282 Method for fabricating thin film transistor Aug. 4, 1998
5776814 Process for doping two levels of a double poly bipolar transistor after formation of second poly layer Jul. 7, 1998
5773349 Method for making ultrahigh speed bipolar transistor Jun. 30, 1998
5773346 Semiconductor processing method of forming a buried contact Jun. 30, 1998
5773358 Method of forming a field effect transistor and method of forming CMOS integrated circuitry Jun. 30, 1998
5773340 Method of manufacturing a BIMIS Jun. 30, 1998
5770490 Method for producing dual work function CMOS device Jun. 23, 1998
5766998 Method for fabricating narrow channel field effect transistors having titanium shallow junctions Jun. 16, 1998
5759885 Method for fabricating CMOSFET having LDD structure Jun. 2, 1998
5753551 Memory cell array with a self-aligned, buried bit line May. 19, 1998
5723356 Fabrication method for semiconductor device Mar. 3, 1998
5721165 Method of forming CMOS circuitry Feb. 24, 1998
5710054 Method of forming a shallow junction by diffusion from a silicon-based spacer Jan. 20, 1998
5696006 Method of manufacturing Bi-MOS device Dec. 9, 1997
5696025 Method of forming guard ringed schottky diode Dec. 9, 1997
5681778 Semiconductor processing method of forming a buried contact and conductive line Oct. 28, 1997
5674777 Method for forming silicon-boron binary compound layer as boron diffusion source in silicon electronic device Oct. 7, 1997
5670417 Method for fabricating self-aligned semiconductor component Sep. 23, 1997
5643806 Manufacturing method for making bipolar device Jul. 1, 1997
5637525 Method of forming a CMOS circuitry Jun. 10, 1997
5635418 Method of making a resistor Jun. 3, 1997
5624863 Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate Apr. 29, 1997
5597741 Process for forming a recrystallized layer and diffusing impurities Jan. 28, 1997
5541137 Method of forming improved contacts from polysilicon to silicon or other polysilicon layers Jul. 30, 1996
5541120 Method of making complementary bipolar polysilicon emitter devices Jul. 30, 1996
5508213 Method of manufacturing a semiconductor device in which a semiconductor zone is formed through diffusion from a strip of polycrystalline silicon Apr. 16, 1996
5494844 Process of fabricating Bi-CMOS integrated circuit device Feb. 27, 1996
5494848 Buried contact trench process Feb. 27, 1996
5464782 Method to ensure isolation between source-drain and gate electrode using self aligned silicidation Nov. 7, 1995
5462888 Process for manufacturing semiconductor BICMOS device Oct. 31, 1995
5407847 Method for fabricating a semiconductor device having a shallow doped region Apr. 18, 1995
5395774 Methods for forming a transistor having an emitter with enhanced efficiency Mar. 7, 1995
5393687 Method of making buried contact module with multiple poly si layers Feb. 28, 1995
5380677 Method for reducing resistance at interface of single crystal silicon and deposited silicon Jan. 10, 1995
5354710 Method of manufacturing semiconductor devices using an adsorption enhancement layer Oct. 11, 1994
5324684 Gas phase doping of semiconductor material in a cold-wall radiantly heated reactor under reduced pressure Jun. 28, 1994
5281552 MOS fabrication process, including deposition of a boron-doped diffusion source layer Jan. 25, 1994
5270249 Fabrication process of a semiconductor device having a reduced parasitic capacitance Dec. 14, 1993
5244533 Method of manufacturing bipolar transistor operated at high speed Sep. 14, 1993
5238849 Method of fabricating semiconductor device Aug. 24, 1993
5236873 Method for contacting a semiconductor component Aug. 17, 1993
5231038 Method of producing field effect transistor Jul. 27, 1993
5213989 Method for forming a grown bipolar electrode contact using a sidewall seed May. 25, 1993

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