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Class Information
Number: 438/555
Name: Semiconductor device manufacturing: process > Introduction of conductivity modifying dopant into semiconductive material > Diffusing a dopant > Laterally under mask opening
Description: Processes wherein the direction of diffusion for the electrically active impurity includes a component parallel to the major surface of the masking layer.

Patents under this class:
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Patent Number Title Of Patent Date Issued
8629026 Source tip optimization for high voltage transistor devices Jan. 14, 2014
8623749 Reduction of stored charge in the base region of a bipolar transistor to improve switching speed Jan. 7, 2014
8461005 Method of manufacturing doping patterns Jun. 11, 2013
8383498 Method for formation of tips Feb. 26, 2013
8110488 Method for increasing etch rate during deep silicon dry etch Feb. 7, 2012
7972948 Method for forming bit lines for semiconductor devices Jul. 5, 2011
7955929 Method of forming a semiconductor device having an active area and a termination area Jun. 7, 2011
7892945 Nanowire mesh device and method of fabricating same Feb. 22, 2011
7858458 CMOS fabrication Dec. 28, 2010
7846823 Masking paste, method of manufacturing same, and method of manufacturing solar cell using masking paste Dec. 7, 2010
7829420 Method of forming a channel termination region using a trench and a channel stopper ring Nov. 9, 2010
7829377 Diamond medical devices Nov. 9, 2010
7811915 Method for forming bit lines for semiconductor devices Oct. 12, 2010
7781871 Structure for reduction of soft error rates in integrated circuits Aug. 24, 2010
7615420 Method for manufacturing indium gallium aluminium nitride thin film on silicon substrate Nov. 10, 2009
7601627 Method for reduction of soft error rates in integrated circuits Oct. 13, 2009
7582537 Zener diode and methods for fabricating and packaging same Sep. 1, 2009
7544592 Method for increasing etch rate during deep silicon dry etch Jun. 9, 2009
7470614 Methods for fabricating semiconductor devices and contacts to semiconductor devices Dec. 30, 2008
7407851 DMOS device with sealed channel processing Aug. 5, 2008
7381635 Method and structure for reduction of soft error rates in integrated circuits Jun. 3, 2008
7354846 Submount substrate for mounting light emitting device and method of fabricating the same Apr. 8, 2008
7192853 Method of improving the breakdown voltage of a diffused semiconductor junction Mar. 20, 2007
7166232 Method for producing a solid body including a microstructure Jan. 23, 2007
7067383 Method of making bipolar transistors and resulting product Jun. 27, 2006
6893947 Advanced RF enhancement-mode FETs with improved gate properties May. 17, 2005
6825122 Method for fabricating a patterned thin film and a micro device Nov. 30, 2004
6780781 Method for manufacturing an electronic device Aug. 24, 2004
6605519 Method for thin film lift-off processes using lateral extended etching masks and device Aug. 12, 2003
6596556 Light emitting diode and a method for manufacturing the same Jul. 22, 2003
6586303 Method for fabricating a mask ROM Jul. 1, 2003
6528398 Thinning of trench and line or contact spacing by use of dual layer photoresist Mar. 4, 2003
6486048 Method for fabricating a semiconductor device using conductive oxide and metal layer to silicide source + drain Nov. 26, 2002
6444548 Bitline diffusion with halo for improved array threshold voltage control Sep. 3, 2002
6410388 Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device Jun. 25, 2002
6368921 Manufacture of trench-gate semiconductor devices Apr. 9, 2002
6303492 Expanded implantation of contact holes Oct. 16, 2001
6294445 Single mask process for manufacture of fast recovery diode Sep. 25, 2001
6204110 Methods of forming an SRAM Mar. 20, 2001
6190979 Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill Feb. 20, 2001
6165870 Element isolation method for semiconductor devices including etching implanted region under said spacer to form a stepped trench structure Dec. 26, 2000
6124167 Method for forming an etch mask during the manufacture of a semiconductor device Sep. 26, 2000
6100173 Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process Aug. 8, 2000
6071762 Process to manufacture LDD TFT Jun. 6, 2000
5998266 Method of forming a semiconductor structure having laterally merged body layer Dec. 7, 1999
5891776 Methods of forming insulated-gate semiconductor devices using self-aligned trench sidewall diffusion techniques Apr. 6, 1999
5856003 Method for forming pseudo buried layer for sub-micron bipolar or BiCMOS device Jan. 5, 1999
5856228 Manufacturing method for making bipolar device having double polysilicon structure Jan. 5, 1999
5700714 Diffusion mask and fabrication method for forming pn-junction elements in a compound semiconductor substrate Dec. 23, 1997
5686322 Process for doping two levels of a double poly bipolar transistor after formation of second poly layer Nov. 11, 1997

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