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Class Information
Number: 438/552
Name: Semiconductor device manufacturing: process > Introduction of conductivity modifying dopant into semiconductive material > Diffusing a dopant > Using multiple layered mask > Having plural predetermined openings in master mask
Description: Processes wherein the multiple layered diffusion mask contains a multitude of desired openings.

Patents under this class:
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Patent Number Title Of Patent Date Issued
8629026 Source tip optimization for high voltage transistor devices Jan. 14, 2014
8461005 Method of manufacturing doping patterns Jun. 11, 2013
8193018 Patterning method for light-emitting devices Jun. 5, 2012
8133755 Avalanche photodiode having controlled breakdown voltage Mar. 13, 2012
8110488 Method for increasing etch rate during deep silicon dry etch Feb. 7, 2012
8097517 Method for manufacturing semiconductor device with improved short channel effect of a PMOS and stabilized current of a NMOS Jan. 17, 2012
8080485 Localized temperature control during rapid thermal anneal Dec. 20, 2011
8003543 Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same Aug. 23, 2011
7964485 Method of forming a region of graded doping concentration in a semiconductor device and related apparatus Jun. 21, 2011
7883973 Method of forming semiconductor wells Feb. 8, 2011
7846760 Doped plug for CCD gaps Dec. 7, 2010
7846823 Masking paste, method of manufacturing same, and method of manufacturing solar cell using masking paste Dec. 7, 2010
7790589 Method of providing enhanced breakdown by diluted doping profiles in high-voltage transistors Sep. 7, 2010
7732341 Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same Jun. 8, 2010
7700469 Methods of forming semiconductor constructions Apr. 20, 2010
7687385 Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same Mar. 30, 2010
7615420 Method for manufacturing indium gallium aluminium nitride thin film on silicon substrate Nov. 10, 2009
7563712 Method of forming micro pattern in semiconductor device Jul. 21, 2009
7544592 Method for increasing etch rate during deep silicon dry etch Jun. 9, 2009
7495347 Ion implantation with multiple concentration levels Feb. 24, 2009
7459334 Method of manufacturing quartz crystal vibrating piece Dec. 2, 2008
7396757 Interconnect structure with dielectric air gaps Jul. 8, 2008
7393794 Pattern formation method Jul. 1, 2008
RE40275 Method for producing a memory cell Apr. 29, 2008
7303949 High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture Dec. 4, 2007
7262127 Method for Cu metallization of highly reliable dual damascene structures Aug. 28, 2007
6955726 Mask and mask frame assembly for evaporation Oct. 18, 2005
6893987 Simple process for fabricating semiconductor devices May. 17, 2005
6878577 Method of forming LDD of semiconductor devices Apr. 12, 2005
6797578 Method for fabrication of emitter of a transistor and related structure Sep. 28, 2004
6780781 Method for manufacturing an electronic device Aug. 24, 2004
6716730 Pattern formation method Apr. 6, 2004
6703266 Method for fabricating thin film transistor array and driving circuit Mar. 9, 2004
6613655 Method of fabricating system on chip device Sep. 2, 2003
6573167 Using a carbon film as an etch hardmask for hard-to-etch materials Jun. 3, 2003
6548385 Method for reducing pitch between conductive features, and structure formed using the method Apr. 15, 2003
6306709 Semiconductor device and manufacturing method thereof Oct. 23, 2001
6248650 Self-aligned BJT emitter contact Jun. 19, 2001
6136656 Method to create a depleted poly MOSFET Oct. 24, 2000
6096591 Method of making an IGFET and a protected resistor with reduced processing steps Aug. 1, 2000
6060330 Method of customizing integrated circuits by selective secondary deposition of interconnect material May. 9, 2000
5904552 Method of resistless patterning of a substrate for implantation May. 18, 1999
5753548 Method for preventing fluorine outgassing-induced interlevel dielectric delamination on P-channel FETS May. 19, 1998
5723354 Solid state image pickup device and manufacturing method therefor Mar. 3, 1998
5686322 Process for doping two levels of a double poly bipolar transistor after formation of second poly layer Nov. 11, 1997
5679586 Composite mask process for semiconductor fabrication Oct. 21, 1997
5198370 Method for producing an infrared detector Mar. 30, 1993
4927772 Method of making high breakdown voltage semiconductor device May. 22, 1990
4837176 Integrated circuit structures having polycrystalline electrode contacts and process Jun. 6, 1989
4692998 Process for fabricating semiconductor components Sep. 15, 1987

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