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Class Information
Number: 438/528
Name: Semiconductor device manufacturing: process > Introduction of conductivity modifying dopant into semiconductive material > Ion implantation of dopant into semiconductor region > Including multiple implantation steps > Providing nondopant ion (e.g., proton, etc.)
Description: Process wherein a nonelectrically active impurity species is implanted into a semiconductor region of the substrate in conjunction with the prior, simultaneous, or subsequent implantation of an electrically active dopant species.










Patents under this class:
1 2 3 4 5 6 7 8 9 10

Patent Number Title Of Patent Date Issued
6482725 Gate formation method for reduced poly-depletion and boron penetration Nov. 19, 2002
6482737 Fabrication method of implanting silicon-ions into the silicon substrate Nov. 19, 2002
6475868 Oxygen implantation for reduction of junction capacitance in MOS transistors Nov. 5, 2002
6475887 Method of manufacturing semiconductor device Nov. 5, 2002
6475908 Dual metal gate process: metals and their silicides Nov. 5, 2002
6465332 Method of making MOS transistor with high doping gradient under the gate Oct. 15, 2002
6465370 Low leakage, low capacitance isolation material Oct. 15, 2002
6461933 SPIMOX/SIMOX combination with ITOX option Oct. 8, 2002
6458430 Pretreatment process for plasma immersion ion implantation Oct. 1, 2002
6451701 Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors Sep. 17, 2002
6451676 Method for setting the threshold voltage of a MOS transistor Sep. 17, 2002
6451672 Method for manufacturing electronic devices in semiconductor substrates provided with gettering sites Sep. 17, 2002
6451657 Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant Sep. 17, 2002
6444522 Method of manufacturing a flash memory device with an antidiffusion region between well regions Sep. 3, 2002
6440805 Method of forming a semiconductor device with isolation and well regions Aug. 27, 2002
6440807 Surface engineering to prevent EPI growth on gate poly during selective EPI processing Aug. 27, 2002
6440826 NiSi contacting extensions of active regions Aug. 27, 2002
6436771 Method of forming a semiconductor device with multiple thickness gate dielectric layers Aug. 20, 2002
6432780 Method for suppressing boron penetrating gate dielectric layer by pulsed nitrogen plasma doping Aug. 13, 2002
6429104 Method for forming cavities in a semiconductor substrate by implanting atoms Aug. 6, 2002
6426278 Projection gas immersion laser dopant process (PGILD) fabrication of diffusion halos Jul. 30, 2002
6426279 Epitaxial delta doping for retrograde channel profile Jul. 30, 2002
6423601 Retrograde well structure formation by nitrogen implantation Jul. 23, 2002
6417082 Semiconductor structure Jul. 9, 2002
6410393 Semiconductor device with asymmetric channel dopant profile Jun. 25, 2002
6410991 Semiconductor device and method of manufacturing the same Jun. 25, 2002
6410409 Implanted barrier layer for retarding upward diffusion of substrate dopant Jun. 25, 2002
6403433 Source/drain doping technique for ultra-thin-body SOI MOS transistors Jun. 11, 2002
6399458 Optimized reachthrough implant for simultaneously forming an MOS capacitor Jun. 4, 2002
6399448 Method for forming dual gate oxide Jun. 4, 2002
6391731 Activating source and drain junctions and extensions using a single laser anneal May. 21, 2002
6372591 Fabrication method of semiconductor device using ion implantation Apr. 16, 2002
6372566 Method of forming a silicide layer using metallic impurities and pre-amorphization Apr. 16, 2002
6362063 Formation of low thermal budget shallow abrupt junctions for semiconductor devices Mar. 26, 2002
6362070 Process for manufacturing a SOI wafer with buried oxide regions without cusps Mar. 26, 2002
6355543 Laser annealing for forming shallow source/drain extension for MOS transistor Mar. 12, 2002
6352912 Reduction of reverse short channel effects by deep implantation of neutral dopants Mar. 5, 2002
6344405 Transistors having optimized source-drain structures and methods for making the same Feb. 5, 2002
6342438 Method of manufacturing a dual doped CMOS gate Jan. 29, 2002
6335262 Method for fabricating different gate oxide thicknesses within the same chip Jan. 1, 2002
6335264 Controlled cleavage thin film separation process using a reusable substrate Jan. 1, 2002
6335253 Method to form MOS transistors with shallow junctions using laser annealing Jan. 1, 2002
6333244 CMOS fabrication process with differential rapid thermal anneal scheme Dec. 25, 2001
6319799 High mobility heterojunction transistor and method Nov. 20, 2001
6294481 Semiconductor device and method for manufacturing the same Sep. 25, 2001
6284660 Method for improving CMP processing Sep. 4, 2001
6281037 Method for the targeted production of N-type conductive areas in diamond layers by means of ion implantation Aug. 28, 2001
6274447 Semiconductor device comprising a MOS element and a fabrication method thereof Aug. 14, 2001
6265317 Top corner rounding for shallow trench isolation Jul. 24, 2001
6265293 CMOS transistors fabricated in optimized RTA scheme Jul. 24, 2001

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