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Class Information
Number: 438/445
Name: Semiconductor device manufacturing: process > Formation of electrically isolated lateral semiconductive structure > Recessed oxide by localized oxidation (i.e., locos) > Preliminary etching of groove > Masking of groove sidewall
Description: Process utilizing a layer in contact with the groove sidewalls which serves as a protective covering during either an etching or oxidation step.










Sub-classes under this class:

Class Number Class Name Patents
438/447 Dopant addition 74
438/446 Polysilicon containing sidewall 61


Patents under this class:
1 2 3 4

Patent Number Title Of Patent Date Issued
6723618 Methods of forming field isolation structures Apr. 20, 2004
6720233 Method of producing trench insulation in a substrate Apr. 13, 2004
6682987 METHODS OF FORMING A TRENCH ISOLATION REGION IN A SUBSTRATE BY REMOVING A PORTION OF A LINER LAYER AT A BOUNDARY BETWEEN A TRENCH ETCHING MASK AND AN OXIDE LAYER IN A TRENCH AND INTEGRATED CIR Jan. 27, 2004
6673635 Method for alignment mark formation for a shallow trench isolation process Jan. 6, 2004
6670691 Shallow trench isolation fill process Dec. 30, 2003
6649490 METHODS FOR FORMING INTEGRATED CIRCUIT DEVICES THROUGH SELECTIVE ETCHING OF AN INSULATION LAYER TO INCREASE THE SELF-ALIGNED CONTACT AREA ADJACENT A SEMICONDUCTOR REGION AND INTEGRATED CIRCUIT Nov. 18, 2003
6649489 Poly etching solution to improve silicon trench for low STI profile Nov. 18, 2003
6613632 Fabrication method for a silicon nitride read-only memory Sep. 2, 2003
6579778 Source bus formation for a flash memory using silicide Jun. 17, 2003
6576957 Etch-stopped SOI back-gate contact Jun. 10, 2003
6566273 Etch selectivity inversion for etching along crystallographic directions in silicon May. 20, 2003
6541361 Plasma enhanced method for increasing silicon-containing photoresist selectivity Apr. 1, 2003
6482715 Method of forming shallow trench isolation layer in semiconductor device Nov. 19, 2002
6479368 Method of manufacturing a semiconductor device having a shallow trench isolating region Nov. 12, 2002
6461981 Method of forming a conformal oxide film Oct. 8, 2002
6451672 Method for manufacturing electronic devices in semiconductor substrates provided with gettering sites Sep. 17, 2002
6429093 Sidewall process for forming a low resistance source line Aug. 6, 2002
6420241 Method for forming an isolation region in a semiconductor device and resulting structure using a two step oxidation process Jul. 16, 2002
6391799 Process for fabricating a structure of semiconductor-on-insulator type in particular SiCOI May. 21, 2002
6323105 Method for fabricating an isolation structure including a shallow trench isolation structure and a local-oxidation isolation structure Nov. 27, 2001
6291315 Method for etching trench in manufacturing semiconductor devices Sep. 18, 2001
6291312 Method for forming pullback opening above shallow trenc isolation structure Sep. 18, 2001
6284626 Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench Sep. 4, 2001
6284625 Method of forming a shallow groove isolation structure Sep. 4, 2001
6251753 Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition Jun. 26, 2001
6238999 Isolation region forming methods May. 29, 2001
6228727 Method to form shallow trench isolations with rounded corners and reduced trench oxide recess May. 8, 2001
6214696 Method of fabricating deep-shallow trench isolation Apr. 10, 2001
6214699 Method for forming an isolation structure in a substrate Apr. 10, 2001
6207532 STI process for improving isolation for deep sub-micron application Mar. 27, 2001
6180488 Method of forming separating region of semiconductor device Jan. 30, 2001
6121110 Trench isolation method for semiconductor device Sep. 19, 2000
6093622 Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD) Jul. 25, 2000
6074927 Shallow trench isolation formation with trench wall spacer Jun. 13, 2000
6027985 Method for forming element isolating film of semiconductor device Feb. 22, 2000
6020230 Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the Feb. 1, 2000
6013561 Method for forming field oxide film of semiconductor device Jan. 11, 2000
6001707 Method for forming shallow trench isolation structure Dec. 14, 1999
5985736 Process for forming field isolation Nov. 16, 1999
5985693 High density three-dimensional IC interconnection Nov. 16, 1999
5976768 Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby Nov. 2, 1999
5972776 Method of forming a planar isolation structure in an integrated circuit Oct. 26, 1999
5972773 High quality isolation for high density and high performance integrated circuits Oct. 26, 1999
5970364 Method of nitride-sealed oxide-buffered local oxidation of silicon Oct. 19, 1999
5963820 Method for forming field oxide or other insulators during the formation of a semiconductor device Oct. 5, 1999
5960301 Method of forming isolation layer of semiconductor device Sep. 28, 1999
5940720 Methods of forming oxide isolation regions for integrated circuits substrates using mask and spacer Aug. 17, 1999
5940719 Method for forming element isolating film of semiconductor device Aug. 17, 1999
5940718 Nitridation assisted polysilicon sidewall protection in self-aligned shallow trench isolation Aug. 17, 1999
5933747 Method and structure for an advanced isolation spacer shell Aug. 3, 1999

1 2 3 4










 
 
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