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Class Information
Number: 438/445
Name: Semiconductor device manufacturing: process > Formation of electrically isolated lateral semiconductive structure > Recessed oxide by localized oxidation (i.e., locos) > Preliminary etching of groove > Masking of groove sidewall
Description: Process utilizing a layer in contact with the groove sidewalls which serves as a protective covering during either an etching or oxidation step.
Sub-classes under this class:
Patents under this class:
| Patent Number |
Title Of Patent |
Date Issued |
| 7413962 |
Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus |
Aug. 19, 2008 |
| 7407890 |
Patterning sub-lithographic features with variable widths |
Aug. 5, 2008 |
| 7393756 |
Method for fabricating a trench isolation structure having a high aspect ratio |
Jul. 1, 2008 |
| 7314810 |
Method for forming fine pattern of semiconductor device |
Jan. 1, 2008 |
| 7273780 |
Semiconductor device having box-shaped cylindrical storage nodes and fabrication method thereof |
Sep. 25, 2007 |
| 7262127 |
Method for Cu metallization of highly reliable dual damascene structures |
Aug. 28, 2007 |
| 7157350 |
Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration |
Jan. 2, 2007 |
| 7094636 |
Method of forming a conductive line |
Aug. 22, 2006 |
| 7084502 |
Microelectromechanical device and method for producing it |
Aug. 1, 2006 |
| 7052972 |
Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting in-process apparatus |
May. 30, 2006 |
| 7049206 |
Device isolation for semiconductor devices |
May. 23, 2006 |
| 7049624 |
Member and member manufacturing method |
May. 23, 2006 |
| 7041573 |
Method for fabricating semiconductor device having trench isolation |
May. 9, 2006 |
| 6991994 |
Method of forming rounded corner in trench |
Jan. 31, 2006 |
| 6958276 |
Method of manufacturing trench-type MOSFET |
Oct. 25, 2005 |
| 6943088 |
Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding |
Sep. 13, 2005 |
| 6794259 |
Method for fabricating self-aligning mask layers |
Sep. 21, 2004 |
| 6787426 |
Method for forming word line of semiconductor device |
Sep. 7, 2004 |
| 6784076 |
Process for making a silicon-on-insulator ledge by implanting ions from silicon source |
Aug. 31, 2004 |
| 6777297 |
Disposable spacer and method of forming and using same |
Aug. 17, 2004 |
| 6746936 |
Method for forming isolation film for semiconductor devices |
Jun. 8, 2004 |
| 6743695 |
Shallow trench isolation method and method for manufacturing non-volatile memory device using the same |
Jun. 1, 2004 |
| 6727158 |
Structure and method for forming a faceted opening and a layer filling therein |
Apr. 27, 2004 |
| 6727161 |
Isolation technology for submicron semiconductor devices |
Apr. 27, 2004 |
| 6727150 |
Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers |
Apr. 27, 2004 |
| 6727142 |
Orientation independent oxidation of nitrided silicon |
Apr. 27, 2004 |
| 6723618 |
Methods of forming field isolation structures |
Apr. 20, 2004 |
| 6720233 |
Method of producing trench insulation in a substrate |
Apr. 13, 2004 |
| 6682987 |
METHODS OF FORMING A TRENCH ISOLATION REGION IN A SUBSTRATE BY REMOVING A PORTION OF A LINER LAYER AT A BOUNDARY BETWEEN A TRENCH ETCHING MASK AND AN OXIDE LAYER IN A TRENCH AND INTEGRATED CIR |
Jan. 27, 2004 |
| 6673635 |
Method for alignment mark formation for a shallow trench isolation process |
Jan. 6, 2004 |
| 6670691 |
Shallow trench isolation fill process |
Dec. 30, 2003 |
| 6649489 |
Poly etching solution to improve silicon trench for low STI profile |
Nov. 18, 2003 |
| 6649490 |
METHODS FOR FORMING INTEGRATED CIRCUIT DEVICES THROUGH SELECTIVE ETCHING OF AN INSULATION LAYER TO INCREASE THE SELF-ALIGNED CONTACT AREA ADJACENT A SEMICONDUCTOR REGION AND INTEGRATED CIRCUIT |
Nov. 18, 2003 |
| 6613632 |
Fabrication method for a silicon nitride read-only memory |
Sep. 2, 2003 |
| 6579778 |
Source bus formation for a flash memory using silicide |
Jun. 17, 2003 |
| 6576957 |
Etch-stopped SOI back-gate contact |
Jun. 10, 2003 |
| 6566273 |
Etch selectivity inversion for etching along crystallographic directions in silicon |
May. 20, 2003 |
| 6541361 |
Plasma enhanced method for increasing silicon-containing photoresist selectivity |
Apr. 1, 2003 |
| 6482715 |
Method of forming shallow trench isolation layer in semiconductor device |
Nov. 19, 2002 |
| 6479368 |
Method of manufacturing a semiconductor device having a shallow trench isolating region |
Nov. 12, 2002 |
| 6461981 |
Method of forming a conformal oxide film |
Oct. 8, 2002 |
| 6451672 |
Method for manufacturing electronic devices in semiconductor substrates provided with gettering sites |
Sep. 17, 2002 |
| 6429093 |
Sidewall process for forming a low resistance source line |
Aug. 6, 2002 |
| 6420241 |
Method for forming an isolation region in a semiconductor device and resulting structure using a two step oxidation process |
Jul. 16, 2002 |
| 6391799 |
Process for fabricating a structure of semiconductor-on-insulator type in particular SiCOI |
May. 21, 2002 |
| 6323105 |
Method for fabricating an isolation structure including a shallow trench isolation structure and a local-oxidation isolation structure |
Nov. 27, 2001 |
| 6291312 |
Method for forming pullback opening above shallow trenc isolation structure |
Sep. 18, 2001 |
| 6291315 |
Method for etching trench in manufacturing semiconductor devices |
Sep. 18, 2001 |
| 6284626 |
Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench |
Sep. 4, 2001 |
| 6284625 |
Method of forming a shallow groove isolation structure |
Sep. 4, 2001 |
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