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Class Information
Number: 438/437
Name: Semiconductor device manufacturing: process > Formation of electrically isolated lateral semiconductive structure > Grooved and refilled with deposited dielectric material > Multiple insulative layers in groove > Conformal insulator formation
Description: Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material including forming an insulative layer which follows the contour of the groove.

Patents under this class:
1 2 3 4 5 6 7 8 9

Patent Number Title Of Patent Date Issued
6066543 Method of manufacturing a gap filling for shallow trench isolation May. 23, 2000
6066544 Isolation regions and methods of forming isolation regions May. 23, 2000
6064105 Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide May. 16, 2000
6063689 Method for forming an isolation May. 16, 2000
6057211 Method for manufacturing an integrated circuit arrangement May. 2, 2000
6057210 Method of making a shallow trench isolation for ULSI formation via in-direct CMP process May. 2, 2000
6054365 Process for filling deep trenches with polysilicon and oxide Apr. 25, 2000
6046088 Method for self-aligning polysilicon gates with field isolation and the resultant structure Apr. 4, 2000
6043136 Trench filling method employing oxygen densified gap filling CVD silicon oxide layer Mar. 28, 2000
6037238 Process to reduce defect formation occurring during shallow trench isolation formation Mar. 14, 2000
6033968 Method for forming a shallow trench isolation structure Mar. 7, 2000
6033970 Method for forming device-isolating layer in semiconductor device Mar. 7, 2000
6030882 Method for manufacturing shallow trench isolation structure Feb. 29, 2000
6027983 Method of manufacturing trench isolate semiconductor integrated circuit device Feb. 22, 2000
6017803 Method to prevent dishing in chemical mechanical polishing Jan. 25, 2000
6010947 Semiconductor device and method for manufacturing Jan. 4, 2000
6008109 Trench isolation structure having a low K dielectric encapsulated by oxide Dec. 28, 1999
6001735 Dual damascene technique Dec. 14, 1999
6001707 Method for forming shallow trench isolation structure Dec. 14, 1999
5994201 Method for manufacturing shallow trench isolation regions Nov. 30, 1999
5989975 Method for manufacturing shallow trench isolation Nov. 23, 1999
5989978 Shallow trench isolation of MOSFETS with reduced corner parasitic currents Nov. 23, 1999
5985735 Trench isolation process using nitrogen preconditioning to reduce crystal defects Nov. 16, 1999
5981357 Semiconductor trench isolation with improved planarization methodology Nov. 9, 1999
5981353 Method of forming a shallow trench isolation region Nov. 9, 1999
5981356 Isolation trenches with protected corners Nov. 9, 1999
5976948 Process for forming an isolation region with trench cap Nov. 2, 1999
5976951 Method for preventing oxide recess formation in a shallow trench isolation Nov. 2, 1999
5968610 Multi-step high density plasma chemical vapor deposition process Oct. 19, 1999
5960299 Method of fabricating a shallow-trench isolation structure in integrated circuit Sep. 28, 1999
5950090 Method for fabricating a metal-oxide semiconductor transistor Sep. 7, 1999
5943578 Method of manufacturing a semiconductor device having an element isolating region Aug. 24, 1999
5943590 Method for improving the planarity of shallow trench isolation Aug. 24, 1999
5940717 Recessed shallow trench isolation structure nitride liner and method for making same Aug. 17, 1999
5937309 Method for fabricating shallow trench isolation structure Aug. 10, 1999
5937308 Semiconductor trench isolation structure formed substantially within a single chamber Aug. 10, 1999
5933749 Method for removing a top corner of a trench Aug. 3, 1999
5933748 Shallow trench isolation process Aug. 3, 1999
5926723 Generation of a loose planarization mask having relaxed boundary conditions for use in shallow trench isolation processes Jul. 20, 1999
5915192 Method for forming shallow trench isolation Jun. 22, 1999
5908318 Method of forming low capacitance interconnect structures on semiconductor substrates Jun. 1, 1999
5904540 Method for manufacturing shallow trench isolation May. 18, 1999
5904539 Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties May. 18, 1999
5897361 Semiconductor device and method of producing same Apr. 27, 1999
5891770 Method for fabricating a high bias metal oxide semiconductor device Apr. 6, 1999
5866466 Methods of fabricating trench isolation regions with risers Feb. 2, 1999
5863828 Trench planarization technique Jan. 26, 1999
5861337 Method for annealing a semiconductor Jan. 19, 1999
5858858 Annealing methods for forming isolation trenches Jan. 12, 1999
5837612 Silicon chemical mechanical polish etch (CMP) stop for reduced trench fill erosion and method for formation Nov. 17, 1998

1 2 3 4 5 6 7 8 9

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