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Class Information
Number: 438/435
Name: Semiconductor device manufacturing: process > Formation of electrically isolated lateral semiconductive structure > Grooved and refilled with deposited dielectric material > Multiple insulative layers in groove
Description: Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with plural insulative layers.










Sub-classes under this class:

Class Number Class Name Patents
438/437 Conformal insulator formation 444
438/436 Reflow of insulator 112


Patents under this class:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Patent Number Title Of Patent Date Issued
8709901 Method of forming an isolation structure Apr. 29, 2014
8686534 Trench isolation structure and method for forming the same Apr. 1, 2014
8679941 Method to improve wet etch budget in FEOL integration Mar. 25, 2014
8673735 Semiconductor device and method for making same Mar. 18, 2014
8673738 Shallow trench isolation structures Mar. 18, 2014
8642419 Methods of forming isolation structures for semiconductor devices Feb. 4, 2014
8609491 Method for fabricating semiconductor device with buried bit lines Dec. 17, 2013
8609480 Methods of forming isolation structures on FinFET semiconductor devices Dec. 17, 2013
8603895 Methods of forming isolation structures for semiconductor devices by performing a deposition-etch-deposition sequence Dec. 10, 2013
8587085 Semiconductor device with trench isolation having a diffusion preventing film and manufacturing method thereof Nov. 19, 2013
8580649 Method for manufacturing semiconductor device Nov. 12, 2013
8580652 Semiconductor device and manufacturing method thereof Nov. 12, 2013
8551861 Semiconductor device and method for manufacturing the same Oct. 8, 2013
8546216 Nonvolatile semiconductor memory device and method of fabricating the same Oct. 1, 2013
8546218 Method for fabricating semiconductor device with buried word line Oct. 1, 2013
8541278 Method for fabricating super-junction power device with reduced miller capacitance Sep. 24, 2013
8536019 Semiconductor devices having encapsulated isolation regions and related fabrication methods Sep. 17, 2013
8530330 Method for manufacturing a semiconductor device capable of preventing the decrease of the width of an active region Sep. 10, 2013
8501562 Fabricating a gate oxide Aug. 6, 2013
8501633 Forming substrate structure by filling recesses with deposition material Aug. 6, 2013
8492241 Method for simultaneously forming a through silicon via and a deep trench structure Jul. 23, 2013
8481431 Method for opening one-side contact region of vertical transistor and method for fabricating one-side junction region using the same Jul. 9, 2013
8470686 Method of increasing deposition rate of silicon dioxide on a catalyst Jun. 25, 2013
8461015 STI structure and method of forming bottom void in same Jun. 11, 2013
8461016 Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation Jun. 11, 2013
8404600 Method for forming fine pitch structures Mar. 26, 2013
8384188 Semiconductor device and fabrication method thereof Feb. 26, 2013
8383489 SOI wafer and method for forming the same Feb. 26, 2013
8383481 Semiconductor memory device and method of manufacturing the same Feb. 26, 2013
8372761 Plasma oxidation processing method, plasma processing apparatus and storage medium Feb. 12, 2013
8367515 Hybrid shallow trench isolation for high-k metal gate device improvement Feb. 5, 2013
8361879 Stress-inducing structures, methods, and materials Jan. 29, 2013
8338264 Methods for forming isolation structures for semiconductor devices Dec. 25, 2012
8318584 Oxide-rich liner layer for flowable CVD gapfill Nov. 27, 2012
8319311 Hybrid STI gap-filling approach Nov. 27, 2012
8294238 Nonvolatile semiconductor memory device with reduced size of peripheral circuit area Oct. 23, 2012
RE43765 Method for fabricating semiconductor device having trench isolation layer Oct. 23, 2012
8278185 Method for forming device isolation layer of semiconductor device and non-volatile memory device Oct. 2, 2012
8264088 Planarized passivation layer for semiconductor devices Sep. 11, 2012
8232179 Method to improve wet etch budget in FEOL integration Jul. 31, 2012
8232180 Manufacturing method of semiconductor device comprising active region divided by STI element isolation structure Jul. 31, 2012
8227901 Mesa type semiconductor device and manufacturing method thereof Jul. 24, 2012
8217472 Semiconductor device with isolation trench liner Jul. 10, 2012
8211779 Method for forming isolation layer in semiconductor device Jul. 3, 2012
8198171 Semiconductor device and fabrication method thereof Jun. 12, 2012
8173516 Method of forming shallow trench isolation structure May. 8, 2012
8173515 Method for manufacturing semiconductor device May. 8, 2012
8163627 Method of forming isolation layer of semiconductor device Apr. 24, 2012
8158488 Method of increasing deposition rate of silicon dioxide on a catalyst Apr. 17, 2012
8148784 Semiconductor device having first and second device isolation layers formed of different insulation materials Apr. 3, 2012

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