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Class Information
Number: 438/430
Name: Semiconductor device manufacturing: process > Formation of electrically isolated lateral semiconductive structure > Grooved and refilled with deposited dielectric material > And deposition of polysilicon or noninsulative material into groove
Description: Process for making electrically isolated laterally spaced semiconductor regions by grooving and refilling with insulative material wherein polysilicon or noninsulative material is deposited into the groove.

Sub-classes under this class:

Class Number Class Name Patents
438/431 Oxidation of deposited material 219

Patents under this class:
1 2 3 4 5 6 7 8 9 10

Patent Number Title Of Patent Date Issued
8710510 High power insulated gate bipolar transistors Apr. 29, 2014
8704041 Methods and compositions for targeted polynucleotide modification Apr. 22, 2014
8673737 Array and moat isolation structures and method of manufacture Mar. 18, 2014
8664080 Vertical ESD protection device Mar. 4, 2014
8659117 Lateral power diode with self-biasing electrode Feb. 25, 2014
8652933 Semiconductor structure having wide and narrow deep trenches with different materials Feb. 18, 2014
8647945 Method of forming substrate contact for semiconductor on insulator (SOI) substrate Feb. 11, 2014
8624266 Silicon carbide substrate, semiconductor device, method of manufacturing silicon carbide substrate and method of manufacturing semiconductor device Jan. 7, 2014
8614137 Dual contact trench resistor in shallow trench isolation (STI) and methods of manufacture Dec. 24, 2013
8603879 Method for fabricating super-junction power device with reduced miller capacitance Dec. 10, 2013
8598012 Method for fabricating semiconductor device with buried gates Dec. 3, 2013
8592284 Semiconductor device and manufacturing method thereof Nov. 26, 2013
8587085 Semiconductor device with trench isolation having a diffusion preventing film and manufacturing method thereof Nov. 19, 2013
8586448 Method and apparatus for forming silicon film Nov. 19, 2013
8552535 Trench shielding structure for semiconductor device and method Oct. 8, 2013
8546243 Dual contact trench resistor and capacitor in shallow trench isolation (STI) and methods of manufacture Oct. 1, 2013
8536018 Maskless inter-well deep trench isolation structure and methods of manufacture Sep. 17, 2013
8524587 Non-uniformity reduction in semiconductor planarization Sep. 3, 2013
8518787 Through wafer vias and method of making same Aug. 27, 2013
8464418 Method for temperature compensation in MEMS resonators with isolated regions of distinct material Jun. 18, 2013
8461661 Locos nitride capping of deep trench polysilicon fill Jun. 11, 2013
8455298 Method for forming self-aligned phase-change semiconductor diode memory Jun. 4, 2013
8453318 Method for making a planar coil Jun. 4, 2013
8455330 Devices with gate-to-gate isolation structures and methods of manufacture Jun. 4, 2013
8436440 Method for forming a back-side illuminated image sensor May. 7, 2013
8431457 Method for fabricating a shielded gate trench MOS with improved source pickup layout Apr. 30, 2013
8415224 Method of fabricating a semiconductor device including forming trenches having particular structures Apr. 9, 2013
8404560 Devices with gate-to-gate isolation structures and methods of manufacture Mar. 26, 2013
8399307 Interconnects for stacked non-volatile memory device and method Mar. 19, 2013
8389391 Triple-gate transistor with reverse shallow trench isolation Mar. 5, 2013
8383488 Method for producing a semiconductor component with two trenches Feb. 26, 2013
8383490 Borderless contact for ultra-thin body devices Feb. 26, 2013
8377796 III-V compound semiconductor epitaxy from a non-III-V substrate Feb. 19, 2013
8378445 Trench structures in direct contact Feb. 19, 2013
8377794 Method of manufacturing semiconductor device, and semiconductor device Feb. 19, 2013
8367499 Method for manufacturing semiconductor device with first and second gates over buried bit line Feb. 5, 2013
8367534 Non-uniformity reduction in semiconductor planarization Feb. 5, 2013
8343879 Method for forming isolation layer of semiconductor device Jan. 1, 2013
8338265 Silicided trench contact to buried conductive layer Dec. 25, 2012
8338873 Semiconductor memory device including active pillars and gate pattern Dec. 25, 2012
8334190 Single step CMP for polishing three or more layer film stacks Dec. 18, 2012
8329553 Method for manufacturing semiconductor device and NAND-type flash memory Dec. 11, 2012
8324715 Semiconductor device and method of manufacturing the same Dec. 4, 2012
8309427 Manufacturing method for FIN-FET having floating body Nov. 13, 2012
8298913 Devices with gate-to-gate isolation structures and methods of manufacture Oct. 30, 2012
8293625 Structure and method for hard mask removal on an SOI substrate without using CMP process Oct. 23, 2012
8288243 Method for fabricating through substrate microchannels Oct. 16, 2012
8268697 Silicon-on-insulator devices with buried depletion shield layer Sep. 18, 2012
8263440 Method for fabricating etching barrier by using shadow effect and method for fabricating one side contact of vertical transistor using the same Sep. 11, 2012
8263474 Reduced defect silicon or silicon germanium deposition in micro-features Sep. 11, 2012

1 2 3 4 5 6 7 8 9 10

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