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Class Information
Number: 438/420
Name: Semiconductor device manufacturing: process > Formation of electrically isolated lateral semiconductive structure > Isolation by pn junction only > Plural doping steps
Description: Process for making an junction isolated laterally spaced semiconductor regions including multiple steps of introducing an electrically active dopant species into semiconductive regions of the substrate.

Patents under this class:
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Patent Number Title Of Patent Date Issued
8710587 Lateral double diffused metal oxide semiconductor device and method of manufacturing the same Apr. 29, 2014
8652930 Semiconductor device with self-biased isolation Feb. 18, 2014
8587025 Method for forming laterally varying doping concentrations and a semiconductor device Nov. 19, 2013
8536659 Semiconductor device with integrated channel stop and body contact Sep. 17, 2013
8513087 Processes for forming isolation structures for integrated circuit devices Aug. 20, 2013
8268697 Silicon-on-insulator devices with buried depletion shield layer Sep. 18, 2012
8017488 Manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations Sep. 13, 2011
7662690 Method of preparing a semiconductor substrate utilizing plural implants under an isolation region to isolate adjacent wells Feb. 16, 2010
7659179 Method of forming transistor using step STI profile in memory device Feb. 9, 2010
7638385 Method of forming a semiconductor device and structure therefor Dec. 29, 2009
7473595 Method for decreasing PN junction leakage current of dynamic random access memory Jan. 6, 2009
7262110 Trench isolation structure and method of formation Aug. 28, 2007
7247544 High Q inductor integration Jul. 24, 2007
7169697 Semiconductor device and manufacturing method of the same Jan. 30, 2007
7163869 Shallow trench isolation structure with converted liner layer Jan. 16, 2007
7105387 Semiconductor device and manufacturing method for the same Sep. 12, 2006
6982193 Method of forming a super-junction semiconductor device Jan. 3, 2006
6977204 Method for forming contact plug having double doping distribution in semiconductor device Dec. 20, 2005
6946339 Method for creating a stepped structure on a substrate Sep. 20, 2005
6927145 Bitline hard mask spacer flow for memory cell scaling Aug. 9, 2005
6821824 Semiconductor device and method of manufacturing the same Nov. 23, 2004
6730569 Field effect transistor with improved isolation structures May. 4, 2004
6699771 Process for optimizing junctions formed by solid phase epitaxy Mar. 2, 2004
6696350 Method of fabricating memory device Feb. 24, 2004
6537893 Substrate isolated transistor Mar. 25, 2003
6444522 Method of manufacturing a flash memory device with an antidiffusion region between well regions Sep. 3, 2002
6440805 Method of forming a semiconductor device with isolation and well regions Aug. 27, 2002
6406974 Method of forming triple N well utilizing phosphorus and boron ion implantations Jun. 18, 2002
6362035 Channel stop ion implantation method for CMOS integrated circuits Mar. 26, 2002
6303463 Method for fabricating a flat-cell semiconductor memory device Oct. 16, 2001
6255190 Method for dielectrically isolated deep pn-junctions in silicon substrates using deep trench sidewall predeposition technology Jul. 3, 2001
6169001 CMOS device with deep current path for ESD protection Jan. 2, 2001
6165868 Monolithic device isolation by buried conducting walls Dec. 26, 2000
6063687 Formation of trench isolation for active areas and first level conductors May. 16, 2000
6057184 Semiconductor device fabrication method using connecting implants May. 2, 2000
6033946 Method for fabricating an isolated NMOS transistor on a digital BiCMOS process Mar. 7, 2000
6010926 Method for forming multiple or modulated wells of semiconductor device Jan. 4, 2000
5985710 Twin well forming method for semiconductor device Nov. 16, 1999
5976921 Method for manufacturing electrostatic discharge protection (ESD) and BiCMOS Nov. 2, 1999
5963798 Fabrication method of CMOS device having buried implanted layers for lateral isolation (BILLI) Oct. 5, 1999
5926704 Efficient method for fabricating P-wells and N-wells Jul. 20, 1999
5895251 Method for forming a triple-well in a semiconductor device Apr. 20, 1999
5891780 Method of fabricating mask ROM using junction isolation Apr. 6, 1999
5780344 Method for fabricating mask ROM semiconductor device with junction isolation Jul. 14, 1998
5766970 Method of manufacturing a twin well semiconductor device with improved planarity Jun. 16, 1998
5705422 Method for forming well of semiconductor device Jan. 6, 1998
5661067 Method for forming twin well Aug. 26, 1997
5629240 Method for direct attachment of an on-chip bypass capacitor in an integrated circuit May. 13, 1997
5624857 Process for fabricating double well regions in semiconductor devices Apr. 29, 1997
5556796 Self-alignment technique for forming junction isolation and wells Sep. 17, 1996

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