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Class Information
Number: 438/418
Name: Semiconductor device manufacturing: process > Formation of electrically isolated lateral semiconductive structure > Isolation by pn junction only > With epitaxial semiconductor formation > Dopant addition
Description: Process for making junction isolated laterally spaced semiconductor regions including a step of introducing an electrically active dopant species into semiconductive regions of the substrate.

Sub-classes under this class:

Class Number Class Name Patents
438/419 Plural doping steps 99

Patents under this class:

Patent Number Title Of Patent Date Issued
8609506 On-chip heat spreader Dec. 17, 2013
8513087 Processes for forming isolation structures for integrated circuit devices Aug. 20, 2013
8309423 High voltage diode with reduced substrate injection Nov. 13, 2012
8293659 Method for fabricating dielectric layer with improved insulating properties Oct. 23, 2012
8258042 Buried layer of an integrated circuit Sep. 4, 2012
8154101 High voltage diode with reduced substrate injection Apr. 10, 2012
7951684 Semiconductor device method of manfacturing a quantum well structure and a semiconductor device comprising such a quantum well structure May. 31, 2011
7951679 Method for fabricating semiconductor device May. 31, 2011
7888232 Method for producing a protective structure Feb. 15, 2011
7723172 Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material May. 25, 2010
7659179 Method of forming transistor using step STI profile in memory device Feb. 9, 2010
7524733 Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same Apr. 28, 2009
7262110 Trench isolation structure and method of formation Aug. 28, 2007
6798015 Semiconductor device and method of manufacturing the same Sep. 28, 2004
6737324 Method for fabricating raised source/drain of semiconductor device May. 18, 2004
6703292 Method of making a semiconductor wafer having a depletable multiple-region semiconductor material Mar. 9, 2004
6693018 Method for fabricating DRAM cell transistor having trench isolation structure Feb. 17, 2004
6649481 Methods of fabricating a semiconductor device structure for manufacturing high-density and high-performance integrated-circuits Nov. 18, 2003
6607972 Method for producing an edge termination suitable for high voltages in a basic material wafer prefabricated according to the principle of lateral charge compensation Aug. 19, 2003
6521508 Method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon process Feb. 18, 2003
6518124 Method of fabricating semiconductor device Feb. 11, 2003
6406973 Transistor in a semiconductor device and method of manufacturing the same Jun. 18, 2002
6319793 Circuit isolation utilizing MeV implantation Nov. 20, 2001
6313000 Process for formation of vertically isolated bipolar transistor device Nov. 6, 2001
6306728 Stable high voltage semiconductor device structure Oct. 23, 2001
6303463 Method for fabricating a flat-cell semiconductor memory device Oct. 16, 2001
6291309 Semiconductor device and method for manufacturing the same Sep. 18, 2001
6274456 Monolithic device isolation by buried conducting walls Aug. 14, 2001
6165868 Monolithic device isolation by buried conducting walls Dec. 26, 2000
5938839 Method for forming a semiconductor device Aug. 17, 1999
5849629 Method of forming a low stress polycide conductors on a semiconductor chip Dec. 15, 1998
5702973 Method for forming epitaxial semiconductor wafer for CMOS integrated circuits Dec. 30, 1997
5508210 Element isolating method for compound semiconductor device Apr. 16, 1996
5451269 Semiconductor memory device including an improved substrate structure and method of fabricating the same Sep. 19, 1995
5334546 Method of forming a semiconductor device which prevents field concentration Aug. 2, 1994
5192712 Control and moderation of aluminum in silicon using germanium and germanium with boron Mar. 9, 1993
5089428 Method for forming a germanium layer and a heterojunction bipolar transistor Feb. 18, 1992
5070031 Complementary semiconductor region fabrication Dec. 3, 1991
4662061 Method for fabricating a CMOS well structure May. 5, 1987
4571275 Method for minimizing autodoping during epitaxial deposition utilizing a graded pattern subcollector Feb. 18, 1986
4512816 High-density IC isolation technique capacitors Apr. 23, 1985
4381957 Method of diffusing aluminum May. 3, 1983
4346513 Method of fabricating semiconductor integrated circuit device utilizing selective etching and epitaxial refill Aug. 31, 1982
4281448 Method of fabricating a diode bridge rectifier in monolithic integrated circuit structure utilizing isolation diffusions and metal semiconductor rectifying barrier diode formation Aug. 4, 1981
4278987 Junction isolated IC with thick EPI portion having sides at least 20 degrees from (110) orientations Jul. 14, 1981
4276099 Fabrication of infra-red charge coupled devices Jun. 30, 1981
4161417 Method of making CMOS structure with retarded electric field for minimum latch-up Jul. 17, 1979
4075043 Liquid phase epitaxy method of growing a junction between two semiconductive materials utilizing an interrupted growth technique Feb. 21, 1978
4056413 Etching method for flattening a silicon substrate utilizing an anisotropic alkali etchant Nov. 1, 1977
4000019 Method of retaining substrate profiles during epitaxial deposition Dec. 28, 1976

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